TSMC is aggressively working on CoPoS (Panel-Level) packaging to replace CoWoS for growing compute demand as Glass Core Substrates take center stage.
Panel-Level Packaging Is The Next Logical Step for TSMC As It Eyes CoPoS "Glass Core Substrate" Technology Over CoWoS
The ever-growing AI and compute demand requires next-generation packaging technologies. Intel and TSMC are aggressively working towards that goal, and glass core substrates are going to be a major part of their trajectories moving forward.
In a recent report by Commercial Times Taiwan, it is reported that TSMC is now aggressively moving towards CoPoS (Chip-On-Panel-on-Substrate) as a replacement to CoWoS (Chip-on-Wafer-on-Substrate), and to achieve this, glass core substrates play a big role, which is why the Taiwan-based semiconductor manufacturing company has accelerated the development and mass production timelines of this technology.
TSMC is aggressively pursuing CoPoS and accelerating the construction of its ecosystem. To surpass the existing physical limits of CoWoS, the ability of glass core substrates to accelerate mass production yield is a crucial factor. Taiwanese manufacturers are actively developing key technologies for glass core substrates and CoPoS process equipment, striving to lead in advanced packaging for AI chips.
The advantage of CoPoS over CoWoS is well documented. The move to larger square/rectangle-shaped wafers (or panels) results in more chips and memory modules than CoWoS's circular wafer design.
A standard CoWoS wafer measures around 300mm while CoPoS wafers can measure up to 750x620mm (TSMC will also have 310x310 and 515x510mm Panel-Level wafers as previously disclosed). This not only allows larger compute dies, but also delivers higher volumes (increased wafer/die utilization rate), at 20-30% lower costs per unit area.
Coupled with advanced packaging solutions, Panel-level packaging enables massive multi-die chip packages. And further on the cost side, silicon is replaced by glass, ensuring high volume & cost-effective production. The first pilot production line for CoPoS has already been set up, and Taiwan experts state that CoPoS with Glass Core Substrates is vital for next-generation high-end chips to meet the supply-demand gap.
TSMC is eyeing a mass production of CoPoS wafers in the coming year, with trial production set to begin in 2027 and mass production aiming for a 2028 timeline. The timeline for CoPoS with glass core substrates is set for 2030+. TSMC Arizona is expected to play a big role in CoPoS production between 2029 and 2030.
Meanwhile, TSMC also plans on leveraging Glass Substrate technology for CoWoS, which is currently in development and provides various enhancements such as lower costs, more die utilization, etc. TSMC is working with Ibiden and Innolux to develop its glass core substrate tech, which will come in a 3-layer design with the glass core sandwiched between two ABF layers.
CoPoS adopts a panel-level packaging that transforms the circle into a square, which can significantly increase the material utilization rate of the original 12-inch circular wafer from less than 70% to more than 90%, solving the problem of geometric waste and soaring costs caused by the maximization of photomask size in ultra-large AI chips after 2028.
These timelines fall in line with what Intel and its partners have already mentioned. Amkor Lead has previously stated that Intel's Glass Substrates tech will be ready for commercialization within three years, and advanced panel-level solutions with Co-Packaged Optics have been showcased already. Intel is eyeing its Rio Rancho facility to become the "Crown Jewel" in terms of production of these glass core substrate packaging technologies.
TSMC and Intel will be the two major players working on Glass Core Substrates moving forward. Intel Foundry successes, and its advanced packaging solution such as EMIB have already found strong adoption among some big customers, and with its acceleration in the field of Glass Core technologies, the company is going to be a prominent player in the Foundry business moving forward.
Meanwhile, reports have already highlighted that AMD will be a key customer of TSMC and its FOPLP (Fan-Out Panel-Level-Packaging) technology & 1.4nm process node for its client-aimed Zen 7 lineup. The adoption of FOPLP and CoPoS will extend beyond just client applications & will have a greater role to play in the AI and Compute-oriented data center markets.
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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