SK hynix announces volume-production of its high-end 12-layer HBM3E memory, driving the transition toward the next era of AI computing.
SK hynix Becomes The First Firm To Announce 12-Layer HBM3E Memory Production, Geared Towards AI Markets
[Press Release]: SK hynix announced today that it has begun mass production of the world's first 12-layer HBM3E product with 36GB, the largest capacity of existing HBM to date. The company plans to supply mass-produced products to customers within the year, proving its overwhelming technology once again six months after delivering the HBM3E 8-layer product to customers for the first time in the industry in March this year.
SK hynix is the only company in the world that has developed and supplied the entire HBM lineup from the first generation (HBM1) to the fifth generation (HBM3E), since releasing the world's first HBM in 2013. The company plans to continue its leadership in the AI memory market, addressing the growing needs of AI companies by being the first in the industry to mass-produce the 12-layer HBM3E.
According to the company, the 12-layer HBM3E product meets the world's highest standards in all areas that are essential for AI memory including speed, capacity, and stability. SK hynix has increased the speed of memory operations to 9.6 Gbps, the highest memory speed available today. If 'Llama 3 70B, a Large Language Model (LLM), is driven by a single GPU equipped with four HBM3E products, it can read 70 billion total parameters 35 times within a second.
SK hynix has once again broken through technological limits demonstrating our industry leadership in AI memory. We will continue our position as the No.1 global AI memory provider as we steadily prepare next-generation memory products to overcome the challenges of the AI era.
- Justin Kim, President (Head of AI Infra) at SK hynix
SK hynix has increased the capacity by 50% by stacking 12 layers of 3GB DRAM chips at the same thickness as the previous eight-layer product. To achieve this, the company made each DRAM chip 40% thinner than before and stacked vertically using TSV technology. The company also solved structural issues that arise from stacking thinner chips higher by applying its core technology, the Advanced MR-MUF process.
This allows to provide 10% higher heat dissipation performance compared to the previous generation and secure the stability and reliability of the product through enhanced warpage controlling.
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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