SanDisk is looking for more innovative solutions to address memory limitations, such as stacking NAND Flash within chips.
Memory Limitations Push DRAM/NAND Maker To Get More Innovative, SanDisk Proposes The Stacking of NAND Flash Within Chips
The rapid rise of AI & the proportional demand for compute has led to the exposure of bottlenecks, which are pushing DRAM and NAND manufacturers into going with the out-of-the-box approach.
In the past, chipmakers called it a day by introducing new memory technologies, and DRAM was the primary component. But the rise in costs, development/yield drawbacks, & increased power have led to a focus on other viable solutions. HBM was developing at a steady pace, but that is rapidly becoming a bottleneck due to shortages.
HBM has other drawbacks too, such as lower capacities, and while DRAM makers are pumping out faster speeds and more capacities each generation, they have so far been unable to keep up with demand. HBM also resides beside the primary chip, meaning there are inter-latency drawbacks.
Then there's NAND, which offers more capacities at a cheaper cost, but it resides further away from the chip, and data transfer is slower. NAND has also not been able to achieve the same levels of speed as DRAM (HBM).
Bridging The Best of DRAM & NAND Together
To overcome this, NAND manufacturer SanDisk laid out its plans for its HBF (High-Bandwidth Flash) solution a while back. HBF is said to use a similar architectural hierarchy as HBM, which is to stack multiple layers of NAND Flash on top of each other. Each layer will be connected using multiple TSVs (Through Silicon Vias), which will fuse all NAND packages into a singular stack. While HBM offers 32-64 GB capacities per stack right now, HBF will scale up to 4 TB capacities.
While this solves the capacity and speed concerns, the future demands for AI and HPC require something more. And that's where SanDisk's most recent patent, "US 12,430,274 B2," comes in. The patent explores the idea of 3D Stacking a NAND Flash tile using CBA (CMOS Bonded Array) underneath the main compute tile, which could be an AI accelerator or a GPU. The solution still uses HBM DRAM on the same interposer, but it serves a different purpose.
It's like shooting down two birds with one stone; the HBM does the memory work that needs to be attended to immediately, while the NAND Flash on the Memory Tile is used for Read/Write ops, and for larger sets of data. The NAND Flash offers wider connections between the compute chip and the memory tile, which offers a reduction in speed, cost, and power.
A processing core includes a multi-core processor integrated directly onto a high bandwidth, high-capacity non-volatile memory. The processor may for example be a large graphics processing unit (GPU) or artificial intelligence (AI) processor. The non-volatile memory may comprise a CBA (CMOS bonded to array) memory tile having a single large NAND memory tile coupled together with a CMOS logic circuit tile. The integrated processor and CBA memory tile may be affixed to an interposer. The processing core may further include stacks of high bandwidth memory (HBM) semiconductor dies affixed to the interposer around one or more sides of the processor and CBA memory tile.
Now, while this future may give us a glimpse at future methodologies that overcome the memory bottlenecks, it should be noted that this is still a patent. A lot of things, such as power draw, the price to manufacturer such a chip (housing both NAND and DRAM on a single package), & more, need to be addressed before we see anything even close to this becoming a reality.
The patent creates a real, examined moat around this processor-on-NAND architecture—especially the wide-interface, through-tile routing that is hard to duplicate. Yet the product rolling toward standardization today follows the simpler, market-ready “beside” approach. The most interesting story is still unfolding: whether SanDisk eventually closes the gap between what it has protected and what it is shipping. The announcement is the headline; the patent is the deeper strategic map.
News Sources: @seti_park , @jimmy_yoasobi
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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