Samsung Testing Its Next-Generation Exynos On The 1.4nm Process, Initial Specifications Boast 96MB Of Cache, Higher Clock Speeds & More

May 6, 2026 at 09:17am EDT
Samsung testing a new Exynos chipset on its 1.4nm process
RUMOR ASSESSMENT

50%

Plausible

The 2nm GAA process will have a couple more iterations before Samsung has confidence in its cutting-edge 1.4nm lithography, but that doesn’t mean the company cannot begin early testing of its next-generation Exynos SoC on the newer manufacturing process. Early specification details reveal that Samsung will bring a new threshold for maximum clock speeds, not to mention the System Level Cache (SLC) boosted to a whopping 96MB.

Bleeding-edge Exynos likely sticking with the same 10-core CPU cluster, with Samsung’s 1.4nm process bringing a 25 percent efficiency gain

The Exynos 2700 is yet to be released, but @SPYGO19726 has shared some juicy details belonging to the Korean giant’s first 1.4nm SoC, even though there have been whispers of Samsung struggling with this technology, forcing it to shift to the 2nm process as it focuses more on yield stability rather than competing with TSMC. However, the initial details reveal that the new Exynos tested on the 1.4nm process will have a 10-core CPU cluster divided into a ‘2 + 4 + 4’ configuration.

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The two Prime cores operate at 4.50GHz, with the performance cores running at 3.80GHz, followed by four efficiency cores at 2.00GHz. However, perhaps the most impressive detail about the unnamed Exynos SoC is its integrated 96MB of System Level Cache, with @SPYGO19726 also mentioning an ultra-wide bus width for minimizing latency between the CPU cores and GPU. SLC helps to lower memory latency and boost bandwidth by storing frequently used data in the cache.

The higher this amount, the faster the overall system will be while also running efficiently since components like the CPU, GPU, NPU, ISP, and others won’t need to be active all the time to send information to the large cache. Unfortunately, the downside is that SLC takes up a large portion of the silicon die, and the bigger that die is, the costlier it is to mass produce the chipset.

It’s important to keep in mind that the highest SLC cache in smartphone silicon is 10MB, and it’s found in the Dimensity 9500, so to bump it up to 96MB will force Samsung to develop a die size that’s incompatible with smartphone form factors. Fortunately, there are other applications that it can be used in, but since these are just the initial specifications, however impressive they might be, we must treat them with a pinch of salt for now.

News Source: @SPYGO19726

About the author: Omar Sohail is a reporter and analyst for Wccftech's mobile section, specializing in the technology and business of the mobile industry. His expertise lies in the intricate hardware supply chain, covering developments in semiconductor manufacturing, chip lithography, and camera sensor technology.

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