Micron Drives DDR5 Memory Adoption with Technology Enablement Program


Micron Technology, today announced a comprehensive DDR5 memory enablement program that will provide early access to technical resources, products, and ecosystem partners. The Technology Enablement Program will aid in the design, development, and qualification of next-generation computing platforms that use DDR5, the most technologically advanced DRAM available.

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Today’s news builds on Micron’s  January announcement of DDR5 RDIMM samples and brings the industry one step closer to unlocking the value in next-generation, data-centric applications. Companies joining Micron in the DDR5 Technology Enablement Program include Cadence, Montage, Rambus, Renesas, and Synopsys.

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DDR5 delivers improvements to performance, density, and reliability at a time when modern data centers need to feed rapidly growing processor core counts with memory bandwidth and meet increasing customer demands for reliability, availability, and serviceability. DDR5 will offer greater than twice the effective bandwidth when compared to its predecessor DDR4, helping relieve this bandwidth-per-core crunch and enabling high performance and improved power management in a wide variety of applications.

“Micron has been driving deep technical engagements with the world’s largest server and hyperscale companies to help them better understand how DDR5 can benefit their unique workloads,” said Tom Eby, senior vice president and general manager of the Compute & Networking Business Unit at Micron. “We’re proud to now extend that collaboration across the entire ecosystem through our Technology Enablement Program to help accelerate time to market for this critical next-generation technology.”

Channel partners also play a very important role in any new technology’s development and adoption. As part of the DDR5 Technology Enablement Program (TEP), Micron will work alongside channel partners like distributors, value-added resellers, and OEMs/ODMs as they bring new and innovative products that use DDR5 to the market.

Rishi Chugh, vice president of Product Marketing, IP Group, Cadence

“DDR5 is primarily about density, making it particularly well-suited for enterprise, cloud and big data applications. Cadence has been collaborating with Micron on DDR5 DRAM for more than two years, enabling Micron DDR5 DRAM market adoption with over 15 licensed customers for Cadence's DDR5 IP.”

Geof Findley, vice president of Sales and Business Development, Montage Technology

“As a leading DDR4 memory logic vendor, Montage Technology is excited to partner with Micron on the launch of high-performance DDR5 RDIMM and LRDIMM. We are pleased to offer a comprehensive portfolio of low-power DDR5 logic devices — including DDR5 RCD, DDR5 DB, DDR5 SPD-Hub, DDR5 PMIC and DDR5 Temperature Sensor — and to help drive quick industry adoption of DDR5 memory.”

Chien-Hsin Lee, vice president and general manager, Integrated Circuits, Rambus

“As the first to deliver a silicon-proven DDR5 memory interface chipset for DDR5 DIMMs, Rambus is excited to enable the DDR5 ecosystem with our RCD and data buffer chips. We are pleased to work with leaders like Micron to deliver high-quality solutions that accelerate the time-to-market and adoption of DDR5 memory in leading-edge data center and cloud systems.”

Rami Sethi, vice president of Data Center Business Division, Renesas

“Renesas has been at the forefront of delivering a full suite of silicon solutions to enable all varieties of DDR5 DIMMs. The strong partnerships cultivated over many years with our ecosystem partners and customers such as Micron are essential to bringing the next generation of computing architectures to the industry.”

John Koeter, senior vice president of marketing and strategy for IP, Synopsys

“As the leading provider of DDR IP, Synopsys has been collaborating with Micron to help mutual customers achieve silicon success through many generations of DDR standards, including DDR5. Synopsys’ silicon-proven DesignWare DDR5 IP with differentiated features such as firmware-based training is validated using Micron’s DDR5 DRAM, offering a low-risk solution. Designers can confidently integrate the DDR controller, PHY, and verification IP solution into their high-performance computing SoCs to meet their data rate, bandwidth efficiency, capacity, and RAS requirements.”