MediaTek’s Work On The Google TPU v7 To Boost Dimensity 9600’s Efficiency

Google's upcoming Ironwood TPU v7 has now emerged as the first viable Application-Specific Integrated Circuit (ASIC) to take on NVIDIA's Blackwell GPUs. This seismic event is, understandably, attracting quite a lot of scrutiny of Google's TPU design process and its partners in that endeavor, including Taiwan's MediaTek, which now stands to translate its experience into real-life efficiency gains for its bespoke chips, starting with the upcoming Dimensity 9600 SoC.

Google's Ironwood TPU v7 and MediaTek's role in it

Before jumping to MediaTek's Dimensity 9600, let's first discuss what all of the brouhaha around the Google Ironwood TPU v7 is all about. Here is everything that we know about the architecture of the new TPUs so far:

1. A dual-chiplet design, where each chiplet contains:
   • 1x TensorCore with a systolic array architecture for highly efficient matrix multiplication operations - which form the backbone of AI workloads, including the training and inference of neural networks - by drastically reducing the number of memory reads and writes required from HBM.
     • The Vector Processing Unit (VPU) handles general-purpose, element-wise operations that are essential for AI models, such as activation functions (like ReLU) and normalizations.
     • Matrix Multiply Unit (MXU) handles matrix multiplication operations.
   • 2x SparseCores, which efficiently handle use-cases requiring an irregular, data-dependent memory access, including when processing ultra-large mathematical structures called embeddings - used to transform large categorical feature values (like a list of word-based vocabulary) into a smaller, dense vector representation, constituting a critical step in many AI operations.
   • 96 GB of high-bandwidth memory (HBM).
2. The two chiplets are connected via a die-to-die (D2D) interconnect that is 6x faster than a 1D inter-chip interconnect (ICI) link.
3. A single TPU rack has 64 chips connected via ICI, providing each chip with 1.2 TB/s of bidirectional ICI bandwidth. This basic 64-chip configuration is called a cube.
4. Multiple cubes are connected using an Optical Circuit Switch (OCS) network to form a superpod, which consists of 9,216 chips and 144 cubes.

As for how Google's new TPU performs, just check the above performance figures. As we noted in a dedicated post recently, the TPU v7 Ironwood is very competitive with NVIDIA's GPUs when it comes to inferencing tasks, which are gaining prominence as the industry shifts away from large, foundational AI models. In fact, the upcoming TPU has a lower Total Cost of Ownership (TCO) while offering performance that is nearly on par with NVIDIA's latest GPUs.

MediaTek's Role In Google's TPU v7 Ironwood

MediaTek played an important role in designing Google's TPU v7 Ironwood, and now stands to distill those takeaways to make its upcoming Dimensity 9600 chip much more efficient.

As per the reports that trickled out in March 2025, Google had tasked MediaTek to design Ironwood's  input/output (I/O) modules to facilitate communication between the processor and peripherals. This constitutes a departure from Google's strategy in recent years, where it designed the entirety of next-gen TPU in a close collaboration with Broadcom.

As per a recent estimation by UBS, MediaTek stands to gain $4 billion from its collaboration with Google on the next-gen TPU.

How MediaTek's work on Google's TPU v7 Ironwood improves prospects for a much more efficient Dimensity 9600 chip

Do note that ASICs and mobile-based Application Processors (APs) such as Dimensity 9600 are inherently different. This means that MediaTek won't be able to translate all of its experience into a usable format for the Dimensity 9600. Nonetheless, the company can still make a number of iterative improvements by:

1. Coming up with a more efficient power gating strategy for the Dimensity 9600 chip, allowing the AP to shut down specific I/O blocks more aggressively when not in use.
2. Improving the Dimensity 9600's voltage scaling, allowing the AP to consume the most efficient quantum of voltage, thereby improving the chip's power consumption metric.
3. Tweaking its existing clock-gating strategies to improve the next-gen chip's battery life and vie for more aggressive power budgets.

Of course, MediaTek is also reportedly working on its own AI chips, where its TPU experience would be of much more relevance. Nonetheless, its mobile APs can also benefit by implementing the tweaks mentioned above. This is, of course, very important as MediaTek has already done away with efficiency cores in its mobile AP architecture.

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