Intel 4th Gen Xeon Sapphire Rapids-SP CPUs To Feature Up To 56 Cores on 10nm Enhanced SuperFin Process & 350W TDP

Apr 7, 2021 at 05:58am EDT
Intel 4th Gen Xeon Sapphire Rapids-SP CPU

Details regarding Intel's 4th Gen Xeon family codenamed Sapphire Rapids-SP have leaked out a day after the launch of the 3rd Gen Xeon family. The Sapphire Rapids-SP family will be replacing the Ice Lake-SP family and will go all on board with the 10nm Enhanced SuperFin process node that will be making its formal debut later this year in the Alder Lake consumer family.

Intel Sapphire Rapids-SP 4th Gen Xeon CPUs Detailed - 10nm Enhanced SuperFin Process Node, Up To 56 Cores & 350W TDP

Update: Videocardz has leaked a Xeon comparison chart, coming directly from Intel, which more or less confirms this information and also along with these, a few other tidbits such as the instruction sets and specific I/O capabilities of the Sapphire Rapids-SP family.

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Intel Sapphire Rapids-SP Xeon Server CPU Specifications. (Image Credits: Videocardz)

In an SKU chart posted by Momomo_US, three Intel Sapphire Rapids-SP Xeon CPUs are disclosed. All three SKUs are engineering samples and come with various core configurations. From what we know so far, Intel's Sapphire Rapids-SP lineup is expected to utilize the Golden Cove architecture & will be based on the 10nm Enhanced SuperFin process node.

The Sapphire Rapids lineup will make use of 8 channel DDR5 memory with speeds of up to 4800 MHz and support PCIe Gen 5.0 on the Eagle Stream platform. The Eagle Stream platform will also introduce the LGA 4677 socket which will be replacing the LGA 4189 socket for Intel's upcoming Cedar Island & Whitley platform which would house Cooper Lake-SP and Ice Lake-SP processors, respectively. The Intel Sapphire Rapids-SP Xeon CPUs will also come with CXL 1.1 interconnect that will mark a huge milestone for the blue team in the server segment.

Coming to the configurations, the top part is started to feature 56 cores with a TDP of 350W. What is interesting about this configuration is that it is listed as a low-bin split variant which means that it will be using a tile or MCM design. The Sapphire Rapids-SP Xeon CPU will be composed of a 4-tile layout with each tile featuring 14 cores each. The other two parts that have been mentioned use a monolithic design. A 24 core part with 225W TDP (Lowest Volume) and a 44 core part with 270W TDP (High Volume + Speed Select) are listed too.

It looks like AMD will still hold the upper hand in the number of cores & threads offered per CPU with their Genoa chips pushing for up to 96 cores whereas Intel Xeon chips would max out at 56 cores if they don't plan on making SKUs with a higher number of tiles.

The Intel Saphhire Rapids CPUs will contain 4 HBM2 stacks with a maximum memory of 64 GB (16GB each). The total bandwidth from these stacks will be 1 TB/s. According to leaked details from AdoredTV, HBM2 and GDDR5 will be able to work together in flat, caching/2LM, and hybrid modes. The presence of memory so near to the die would do absolute wonders for certain workloads that require huge data sets and will basically act as an L4 cache.

The platform would be competing against AMD's Zen 4 based EPYC Genoa lineup which would also be moving to a newer platform known as SP5. AMD has promised new memory along with new capabilities for the Genoa lineup which would include support for 8-Channel DDR5, up to 80 PCIe 5.0 lanes, and more. The platform itself would be scalable up to 8 sockets which means that we can see core counts of up to 448 and up to 996 threads on a single server (using 56 core chips).

Currently, AMD's EPYC CPUs demolish Intel in terms of performance per watt, a number of cores/threads, feature set, and total cost of operation with major players in the server segment switching their cloud datacenters to AMD's EPYC CPUs. It remains to be seen if Intel can make a complete or even a partial recovery of its Xeon segment with Sapphire Rapids. For now, Intel is focusing on a launch for its Sapphire Rapids Xeon Scalable family in 2022 but a volume ramp is not expected until early 2022.

Intel Xeon CPU Families (Preliminary):

Family BrandingCoral RapidsDiamond RapidsClearwater ForestGranite RapidsSierra ForestEmerald RapidsSapphire RapidsIce Lake-SPCooper Lake-SPCascade Lake-SP/APSkylake-SP
Process NodeIntel 14A?Intel 18A-PIntel 18AIntel 3Intel 3Intel 7Intel 710nm+14nm++14nm++14nm+
Platform NameTBDIntel Oak StreamIntel Birch StreamIntel Birch StreamIntel Mountain Stream
Intel Birch Stream
Intel Eagle StreamIntel Eagle StreamIntel WhitleyIntel Cedar IslandIntel PurleyIntel Purley
Core ArchitectureTBDPanther Cove-XDarkmontRedwood CoveSierra GlenRaptor CoveGolden CoveSunny CoveCascade LakeCascade LakeSkylake
MCP (Multi-Chip Package) SKUsYesYesYesYesYesYesYesNoNoYesNo
SocketTBDLGA XXXX / 9324LGA 4710 / 7529LGA 4710 / 7529LGA 4710 / 7529LGA 4677LGA 4677LGA 4189LGA 4189LGA 3647LGA 3647
Max Core CountTBDUp To 192 P-CoresUp To 288Up To 128Up To 288Up To 64?Up To 56Up To 40Up To 28Up To 28Up To 28
Max Thread CountTBDUp To 192Up To 288Up To 256Up To 288Up To 128Up To 112Up To 80Up To 56Up To 56Up To 56
Max L3 CacheTBDTBDTBD480 MB L3108 MB L3320 MB L3105 MB L360 MB L338.5 MB L338.5 MB L338.5 MB L3
Memory SupportTBDUp To 16-Channel DDR5-9000+Up To 12-Channel DDR5-8000Up To 12-Channel DDR5-6400
MCR-8800
Up To 12-Channel DDR5-6400Up To 8-Channel DDR5-5600Up To 8-Channel DDR5-4800Up To 8-Channel DDR4-3200Up To 6-Channel DDR4-3200DDR4-2933 6-ChannelDDR4-2666 6-Channel
PCIe Gen SupportPCIe 6.0PCIe 6.0PCIe 5.0 (96 Lanes)PCIe 5.0 (136 Lanes)PCIe 5.0 (88Lanes)PCIe 5.0 (80 Lanes)PCIe 5.0 (80 lanes)PCIe 4.0 (64 Lanes)PCIe 3.0 (48 Lanes)PCIe 3.0 (48 Lanes)PCIe 3.0 (48 Lanes)
TDP Range (PL1)TBDTBDUp To 500WUp To 500WUp To 350WUp To 350WUp To 350W105-270W150W-250W165W-205W140W-205W
3D Xpoint Optane DIMMTBDTBDN/ADonahue PassN/ACrow PassCrow PassBarlow PassBarlow PassApache PassN/A
CompetitionTBDAMD EPYC VeniceAMD EPYC TurinAMD EPYC TurinAMD EPYC BergamoAMD EPYC Genoa ~5nmAMD EPYC Genoa ~5nmAMD EPYC Milan 7nm+AMD EPYC Rome 7nmAMD EPYC Rome 7nmAMD EPYC Naples 14nm
Launch2028-20292027202620242024202320222021202020182017

About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.

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