Intel is rumored to be integrating Panther Lake's memory controller & compute die into a single package to address the latency issues in current architectures.
Intel Will Seemingly Experiment With Panther Lake When It Comes To Fixing Latency Issues & Enhancing D2D Interconnect By Incorporating the Memory Controller Back To The Compute Tile, But Nova Lake Might Be Reverting It Back
Well, it looks like Team Blue isn't satisfied with existing tile configurations and is probably looking to switch things up with the release of its next-gen mobile SoCs, with a major change expected to occur with the IMC (Integrated Memory Controller) and the Compute die.
The renowned leakers kopite7kimi and Jaykihn have disclosed that Intel plans on putting the IMC and compute die into a single package in an attempt to fix performance and efficiency issues encountered with lineups such as the Arrow Lake, and it is said to be more of a "hit and trial" move.
Although PTL will reintegrate IMC into the compute die, NVL will once again separate and optimize it.
— kopite7kimi (@kopite7kimi) October 26, 2024
Subsystems traditionally located on a separate SOC tile are moved to the compute tile in PTL due to the lack of a dedicated SOC tile.
The lack of a dedicated SOC tile is due to scale.
— Jaykihn (@jaykihn0) October 26, 2024
With Intel's Arrow Lake, the IMC and Compute die are presented as two separate entities, and with the IMC being an off-die solution, data transfer has become much more inefficient now. It had to travel across dies to reach the memory controller from the Compute die, indeed creating higher latencies, which were prominent with Arrow Lake. With Intel potentially combining the IMC onto the Compute Die, we will witness reduced latency, given that data wouldn't need to travel across die-to-die, and instead, it will be an instantaneous process.
Given that the IMC moves to the Compute Die, along with other sub-systems, Intel might exclude the SoC tile with Panther Lake due to its scale, since through this, not only can the company reduce design complexities and enhance scalability but achieve desired performance targets as well, which is why this move hasn't been made with existing architectures, notably Intel's Arrow Lake.
It won't be wrong to say that with the debut of Panther Lake, Intel is expected to bring significant design changes to Panther Lake, but interestingly, these changes are rumored to be reverted with Nova Lake. This is said to be because Nova Lake will once again bring back the SoC tile.
This is why, as I mentioned above, Intel's IMC and Compute Die move will be a "hit and trial", since the company is probably in pursuit of enhancing its current D2D interconnects, probably putting them on par with competitors such as AMD, with their Infinity Fabric. Panther Lake will act as grounds for Intel to reduce its dependency on the interconnect. With Nova Lake, well, the firm will present a round of optimizations on the interconnect, hence going back and forth to "pitch" these changes as generational modifications.
It is important to note that these are just mere rumors for now, and Intel hasn't disclosed anything officially, but with the seemingly disappointing ARL performance, Team Blue will be looking to switch things up.
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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