APX or Advanced Performance Extensions are the next evolution of x86 as Intel & AMD co-develop new standards for the architecture.
APX Expands the x86 Instruction Set, Bringing Faster Performance & New Features That Will Benefit Both Intel and AMD's Next-Gen Chips
Two days ago, we talked about ACE (AI Compute Extensions), which is a unified instruction set that aims to increase matrix-multiply performance for next-gen x86 chips. ACE is just one part of the grander scheme in which both Intel and AMD are working together to evolve the x86 architecture under a single unified framework through the recently established x86 EAG or Ecosystem Advisory Group.
Now, the EAG is sharing more details on APX (Advanced Performance Extensions). APX is being called the next step in the evolution of the x86 architecture, and what it does is allow the entire x86 instruction set to access more registers. Registers are small yet extremely fast storage units within the CPU that hold data, instructions, and memory addresses for work that is being done right now. The instruction set having access to more registers is beneficial to the processor's performance.
ACE also adds new features which improved the general-purpose performance. The new extensions also improve performance in an efficient manner across various workloads, and the most important thing is that they do so without a significant increase in silicon area or power consumption of the core. So you can virtually have the same core size/power and achieve higher performance.
Coming back to registers, APX doubles the number of General-Purpose Registers (GPRs) from 16 to 32. This makes the updated x86 architecture a great target for compilers since the compiler can now keep more data and values inside the registers.
| Feature / Improvement | Before APX | With APX | Key Benefit |
|---|---|---|---|
| General-Purpose Registers (GPRs) | 16 registers | 32 registers (doubled) | Compilers can keep more data in fast registers instead of slow memory |
| Memory Operations | Higher number of loads/stores | 10% fewer loads 20% fewer stores | Faster code + significantly lower power usage |
| Instruction Forms | Mostly destructive (overwrites source) | New non-destructive versions | Fewer temporary copies, simpler & faster code |
| Conditional Execution | Limited (CMOV/SET only) | Conditional Load, Store, Compare/Test + flag suppression | Much wider use of if-conversion → fewer branches & mispredictions |
| Stack Operations | Single register PUSH/POP | New PUSH2 / POP2 instructions | Transfer two registers with one memory operation (faster function calls) |
| Code Density | Baseline | Similar to existing binaries | No significant increase in program size |
| Power & Silicon Cost | - | Minimal increase | Performance gains without higher power or cost |
| Compatibility | - | Full interoperability with legacy code | 10% fewer loads, 20% fewer stores |
Just for code compiling, APX reduces the loads by 10% and stores by 20% versus a code compiled for an x86-64 target. So APX is not just offering faster access to registers, but it also consumes significantly lower dynamic power than load/store operations within the chip. All of this evaluation was done within SPEC GPU 2017 integer benchmark using a prototype simulation. Actual x86 chip results with APX will vary, but it gives an idea of what to expect with APX.
What makes APX particularly impressive is how it respects the past while preparing for the future. Legacy software continues to work seamlessly alongside new APX-enabled code, and the architecture’s flexible design continues to prove why x86 has remained dominant for so long.
As AI, data processing, and everyday computing grow more demanding, extensions like APX ensure that x86 will keep delivering better performance and efficiency for years to come. In a world that increasingly runs on silicon, this continued evolution means faster, smarter, and more power-conscious computers for everyone. The x86 story is far from over.
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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