Intel Lays Down 2019-2029 Manufacturing Roadmap – 1.4nm in 10 Years, 2 Year Cadence with Back Porting on Advanced ++ Nodes

Dec 10, 2019

Back in May, Intel unveiled their process roadmap, highlighting their target plans up till 2023, but an even more detailed manufacturing roadmap has been revealed by Anandtech which shows a process roadmap path all the way up to 2029.

Intel Manufacturing Roadmap For The Next 10 Years Unveiled - 7nm in 2021, 5nm in 2023, 3nm in 2025, 2nm in 2027 and 1.4 nm in 2029, Brand New Features and Back Porting

The roadmap is stated to have been unveiled at the IEEE International Electron Devices Meeting by one of Intel's partners who stated that the said slide was first showcased by Intel themselves back in September. Intel already gave us a deep dive of their 7nm process plans but this slide goes even further than that. It's a 10-year roadmap for what's to come so let's see what Intel has to offer us in the coming years.

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Intel's Process and Manufacturing Roadmap for the next 10 years shows 10nm, 7nm, 5nm, 3nm, 2nm, and 1.4nm. (Image Credits: Anandtech)

10nm to 1.4nm in The Next 10 Years

Starting off with the process roadmap, Intel will be following a 2-year cadence for each major node update. We got a soft launch of 10nm (10nm+) in 2019 which will be followed by 7nm in 2021, 5nm in 2023, 3nm in 2025, 2nm in 2027 and 1.4nm in 2029. What's interesting here is that this 2-year cadence is referred to as the optimal cost-performance path by Intel themselves. So it would be Intel's priority to follow this path, but there's also a yearly cadence for the + / ++ nodes that offer more performance leverage and scalability opportunities on an existing node.

Before we talk about the optimized nodes for each process, we should focus on the key features that each major node update has to offer. For 7nm, Intel is saying the biggest feature is that it is made using EUV (Extreme ultraviolet lithography) technology. Similarly, all other major nodes will come with new features, but Intel hasn't explicitly stated what new features we could expect. At the same time as Intel introduces their 10nm++ products, they will also have production and launch planned for their next-gen 7nm process node. The 10nm and 7nm nodes were already detailed by Intel during their 2019 Investors Meeting.

Intel 10nm, 10nm+ and 10nm++

Starting off with the 10nm family, Intel has clarified that their 10nm process node can deliver some major enhancements to performance per watt. Compared to 14nm++, the first iteration of 10nm is shown to be a good leap in efficiency and Intel plans to provide enhanced variants of 10nm moving forward with 10nm+ in 2019, 10nm++ in 2020, and 10nm+++ in 2021. Some of the major upgrades that 10nm would deliver include:

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  • 2.7x density scaling vs 14nm
  • Self-aligned Quad-Patterning
  • Contact Over Active Gate
  • Cobalt Interconnect (M0, M1)
  • 1st Gen Foveros 3D Stacking
  • 2nd Gen EMIB

Intel 7nm, 7nm+ and 7nm++

At the same time as Intel introduces their 10nm+++ products, they will also have production and launch planned for their next-gen 7nm process node. Intel would continue to offer optimizations of the 7nm process node with 7nm+ in 2022 and 7nm++ in 2023. Just like 10nm, 7nm will deliver a good list of enhancements over 10nm which will include:

  • 2x density scaling vs 10nm
  • Planned intra-node optimizations
  • 4x reduction in design rules
  • EUV
  • Next-Gen Foveros & EMIB Packaging

Do note that 10nm is the only process with a +++ optimization since it is already on 10nm+ in 2019. 1.4nm in 2029 looks to be very promising but Intel has had previous roadmaps stating that said we would get 10nm by 2015 and nm by 2017. But, more recently, Intel's CEO, Bob Swan, stated that his company is all set to tackle TSMC with their first 7nm products tackling TSMC's 5nm by Q4 2021 and expects to hit 5nm which he states is equivalent to TSMC's 3nm node by the second half of 2024 and product availability in 2025.

Back Porting To Each Tail-End Optimization Node

The slide also talks about back porting which has been one of the interesting topics to discuss in recent months considering all the ruckus surrounding 14nm and 10nm nodes. Each major node has been shown to include at least two optimizations. 10nm+ will get 10nm++ and 10nm+++, 7nm will get 7nm+ (2022) and 7nm++ (2023), 5nm will get 5nm+ (2024) and 5nm++ (2025), 3nm will get 3nm+ (2026) and 3nm++ (2027) while 2nm will also get 2nm+ (2028) and 2nm++ (2029). There's no optimized path for 1.4nm mentioned but then again, this slide only covers a 10-year roadmap so you can in the least expect an optimized node path for 1.4nm too.

So each major node will be followed by an optimized '+' node in the coming year and a further tail-end optimized '++' node after that. Here's the interesting thing, the '++' or in the case of 10nm, +++ node, will launch alongside the next major node. The optimized node will have some advantages over the new node such as frequency and scalability from the previous two updates along with a higher number of yields.

So here, Intel can decide to make some interesting choices as they have multiple paths to choose from on each node generation. Now, given the timeframe of this roadmap, Intel may already have decided what's next for 10nm and 7nm.

A picture a wafer from Intel's foundry that was fabricated on the 14nm process.

Intel also talks about back porting on an older yet optimized node. A 7nm product can be back ported to 10nm+++, a 5nm product can be back ported to 7nm++, a 3nm product can be back ported to 3nm++ and a 2nm product can be back ported to 3nm++. There's no back porting mentioned for the 1.4nm node.

There have been recent rumors and talks regarding Intel back porting a 10nm++ product (Tiger Lake) to 14nm+++ (Rocket Lake). Substantial evidence has been found, but since the product is aiming a 2021 launch, there's no official word from Intel on the matter. But, given that this roadmap talks about back porting, we may indeed see Rocket Lake CPUs featuring a back port of the Willow Cove cores that are to utilize a 10nm++ node on the mobility platform.