Industry sources rumor TSMC that the semiconductor giant may lower the prices for the N3, or 3nm-class fab process series chips, to increase adoption by other companies, such as tech giants AMD, NVIDIA, MediaTek, and Qualcomm. Achieving this goal will take some time and a fair amount of risk, but it would open the door and offer more opportunities for adoption outside of Apple, one of the largest clients of N3B technology from TSMC.
Industry insiders reveal that TSMC is researching decreasing costs of 3nm process technology to acquire more clients like AMD & NVIDIA
The difficulty TSMC is facing now is the cost of manufacturing the new N3 technology. N3 utilizes EUV (extreme ultraviolet) lithography within twenty-five layers, and EUV scanners, depending on the configuration, can cost between $150 million to $200 million, according to China Renaissance Capital Group. And the foundry price of 3nm technology surpasses $20,000 for each wafer.
AMD has previously mentioned that the company intends to utilize the 3nm process for the Zen 5 microarchitecture, but this won't happen until the second half of 2024 at the earliest, while NVIDIA is aiming to use the N3 technology in its future Blackwell-based graphics cards. Liu Deyin, CEO of TSMC, has reported that the logic density of the fab process for 3nm will heighten to sixty percent, with power consumption levels lowering by as much as thirty-five percent at identical speeds.
We believe the meaningful [N3] ramp-up will be in 2H 2023 when the optimized version, N3E, will be ready. Its major customers in HPC (i.e., AMD, Intel), smartphone (i.e., QCOM, MTK) and ASIC (i.e., MRVL, AVGO, GUC) will likely stay in N4/5 and choose N3E as their maiden N3 class foray, in our view. Meanwhile, we believe the baseline N3 (aka N3B) adoption will be largely limited to Apple products.
— Szeho Ng, analyst, China Renaissance Capital Group
One of TSMC's N3 process nodes, the N3E, currently utilizes EUV lithography in only 19 layers. This lowers the overhead for manufacturing as the production is less complex and leads to lower costs than other process nodes, such as N3P, N3S, and N3X processes. It is also less risky to decrease the purchasing price as the manufacturing is not as intensive. And, with no apparent benefit in SRAM cell scaling compared to the N5 process technology, increased sizes for the chip dies would be present in both N3 and N3B process technologies.