Being limited to older-generation DUV equipment hasn’t deterred Huawei’s efforts to develop and mass produce competitive chipsets, as the Kirin 2026 will be a prime example of the company’s next-generation packaging. Now, in the latest paper, the Chinese giant has detailed how a hybrid bonding process will allow for SoCs to flaunt a 3D stacking approach, which is the first step of removing one of the major obstacles of mobile silicon innovation; lack of access to advanced lithography.
Despite having no access to advanced chipmaking equipment, Huawei’s mastery in smartphone chipset packaging for the Kirin 2026 looks promising
During Huawei’s LogicFolding Design presentation, the company previewed how it would be possible to fabricate chips with vertically-stacked components, increasing transistor density and efficiency without the use of specialized EUV machinery and cutting-edge lithography. In the latest paper, the Kirin 2026 is illustrated to feature a hybrid bonding technique, with the image below showing dense vertical interconnects between layers.
This approach not only boosts performance but also efficiency in future mobile chips, making them suitable for a variety of uses, including running on-device AI. With layers stacked on top of one another, data can travel over micrometers rather than millimeters, substantially increasing communication speeds among the CPU, GPU, NPU, DRAM, and others.
The reduced distance also means that less power is utilized in pushing electrical signals through long wire traces, increasing bandwidth as a result. Given Huawei’s limitations under U.S. sanctions, this hybrid bonding technique is an excellent approach to circumvent the technical challenges of being forced to mass-produce chips on SMIC’s 7nm process.
In fact, Huawei isn’t the only one that has realized the limitations of current-generation packaging, as we’ve already witnessed how older PoP (Package-on-Package) technologies are limiting the SoC’s ability to deliver peak performance. Companies like Samsung appear to keep the DRAM separate from the silicon die with its Exynos 2700, and to cool the chipset, there’s going to be a copper heatsink on top called Heat Pass Block.
Similar to Exynos 2700, Apple’s A20 Pro will utilize Wafer-Level Multi-Chip Module Packaging (WMCM), with the SoC having direct contact with a large vapor chamber to effectively dissipate heat. Seeing these unique methods, do you think Huawei’s LogicFolding Design is superior or inferior? Let us know in the comments.
About the author: Omar Sohail is a reporter and analyst for Wccftech's mobile section, specializing in the technology and business of the mobile industry. His expertise lies in the intricate hardware supply chain, covering developments in semiconductor manufacturing, chip lithography, and camera sensor technology.
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