Cut Off From EUV By US Sanctions, Huawei Is Redefining Moore’s Law Itself — And A Top Chip Analyst Isn’t Buying It

After Huawei made a big announcement earlier this week about its Tau scaling technology, through which it aims to achieve a transistor density similar to the 14 Angstrom (14A) manufacturing process technologies from leading chip manufacturers such as TSMC and Intel, semiconductor analyst Dr. Ian Cutress believes that the announcement compares unrelated aspects of a chip's performance specifications. He discussed the announcement in detail in the TechTechPotato podcast and added that the firm's research paper outlining its Tau scaling technology appeared to be written with AI.

Huawei's Tau Scaling Technology Has Been Researched For Decades, Says Chip Expert

Cutress started his analysis of Huawei's latest announcement by discussing Moore's Law. Moore's Law, in the semiconductor industry, outlines that the number of transistors in a chip doubles every two years while the cost is halved. The expert believes that since US sanctions have prevented Huawei from accessing the latest Extreme Ultraviolet (EUV) lithography equipment, it has been forced to redefine the parameters of chip performance and ignore Moore's Law:

"Huawei's opinion, because they no longer have access to the leading edge EUV, and High NA EUV, because they can't TSMC, or Samsung, or Intel because of US sanctions, is that we need to redefine what our goals are. And their argument is that we're gonna redefine this by ignoring Moore's Law, because we can't compete with that. . .but talk about Tau scaling."

He added that according to Tau scaling, Huawei can claim improvements in performance by improving the entire system, the chip or other components. As a result, the density of more transistors in a chip doesn't matter. According to him, what Huawei is "trying to say is, we think Moore's Law is too narrow focused. Yet Moore's Law has been a proxy. . .for decades."

Advanced lithography machines, such as the EUV equipment that US sanctions have prevented Huawei from utilizing, allow chip manufacturers to print minute circuits on a chip. These circuits enable a growth in transistor density. While Cutress believes that Tau scaling isn't a bad idea, if he were advising Huawei, he would ask the firm to "perhaps be a bit more humble about it because you're not redefining the view. You're refocusing the view."

Huawei's Tau Scaling Concept Has Been Researched By Intel & AMD For Years, Says Chip Expert

Cutress then went on to explain hybrid bonding and the concept of stacking a chip-on-chip. Showing a presentation slide from AMD from 2021, he outlined that back then, "the concept of stacking chip-on-chip was just starting to become reality." He added that it had already "been in the works ten years, right. EMIB, the initial thoughts and patents filed on EMIB were I think back in 2008."

EMIB is Intel's Embedded Multi-die Interconnect Bridge technology, and it connects multiple chip dies side by side to lower manufacturing costs. According to Cutress, "we're talking about here hybrid bonding." Compared to traditional technologies, hybrid bonding removes. microbumps from the process and the first productization of hybrid bonding from TSMC and AMD had a 9 micron pitch. The pitch, according to Cutress, is "the distance between the center of two connections is 9 microns."

The pitch complexity increases as deeper elements of a chip rely on hybrid bonding. Cutress explained:

"Now as you go down, you need finer and finer and finer pitches. You need smaller and smaller micron sized pitches. And the reason why that is, is because every time you go over these connections, you encounter resistance and capacitance. And you have to overcome that. And the way you overcome that is by more and more connections running at lower and lower frequency."

Both TSMC and Intel have roadmaps that reduce the pitch to as much as four micron pitches, with research also indicating at the potential of tens of nanometers for pitches. However, Cutress cautioned that "The biggest problem between research and productization, is moving it into volume. Cause you can do it once in a lab, fine, doing it ten million times in a facility, is, problematic."

Huawei's Transistor Density Claim For Tau Scaling Is Misleading, Says Expert

Another constraint when it comes to hybrid bonding is the energy required during production. Cutress outlined that he was at a show where Dutch chip manufacturing equipment giant ASML showed off its hybrid bonding solutions. He explains that "the amount of energy you need to hybrid bond is per square centimeter is ten times more than you need for leading edge EUV 2nm transistors." The higher energy means that not only is production slower but it also means that good yields are harder to achieve, according to him.

Logic-on-logic stacking, in semiconductor production, means that chips responsible for computing software, such as CPUs and GPUs, are placed on top of each other. Tying his earlier explanation of hybrid bonding and pitch sizes with Huawei's announcement, Cutress remarked:

"Logic stacking from Huawei is 3D stacking, in the conceptual sense, but instead of having SRAM on logic or logic on SRAM. . .their paper is saying we're doing logic on logic and we're doing it at a 2 micron pitch. Which would be market leading significantly."

The expert then aimed at Huawei's claim of achieving transistor density through Tau scaling that is equivalent to the latest manufacturing technologies of Intel and TSMC. He explained that when discussing density "we're talking about transistors per unit area, not per unit volume, per unit area. And that's what we're calling a density. It's a metric that has existed from the beginning of making chips because pretty much every chip we make is monolithic."

Chip Expert Finds Similarities To AI Text In Huawei's Tau Scaling Paper

Cutress added that if after you stack logic on logic, your total 2D space is now two layers while the planar dimensions of the hip are the same. According to him:

"So if you're saying transistors per millimeter are you talking about the floor plan or the silicon used? And the thought experiment I put on twitter was if you build a bungalow, a one floor house, with three bedrooms, that means you have three bedrooms per unit house. If you now build a second story on that, with another three bedrooms, has your density increased?"

The correct answer, according to him, is a yes in urban planning and a no in the construction industry. According to him, what Huawei is doing is "the urban planning equivalent whereas the rest of the industry is following the construction method."

Finally, his focus then shifted to Huawei's Tau scaling research paper. Cutress, after reading the introduction, believes that the paper might be written by AI due to indicators such as "shorty stubby sentences" being present. While he admitted that AI might have played a role in translation, the expert added that such translations are also accompanied by language errors. He also believes that the paper uses a lot of words typically used by AI software.

Cutress concluded his argument by remarking:

"The problem that this whole story has, is, not that it's unbelievable. Right. This whole thing about logic bonding, logic splitting, has been on roadmaps forever. The fact that Tao scaling now just encompasses everything rather than just logic scaling isn't changing anything. The big breakthrough here is Huawei claiming sub 2 micron hybrid bonding and logic on logic."

He added: "Because they haven't had access to logic, they've decided to pull one of the other threads a lot earlier than everybody else. You still need to scale that in terms of manufacturing." " It's, you're arguing apples and oranges on that front," according to him.

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