AMD Zen 3 Microarchitecture to Be Unveiled at CES 2020


In a publication from a Taiwanese newspaper, AMD is set to unveil some details about Zen 2's successor, Zen 3, at CES 2020. AMD's Lisa Su will formally address the matter, primarily focusing on Ryzen 4000, 4th Generation Ryzen Threadripper, and EPYC Rome's successor, Milan.

AMD Zen 3 - 'A Completely New Architecture'

Back in mid-November, we reported Zen 3 will be a complete redesign of the Zen architecture rather than the evolutionary improvements seen between Zen 1, the process shrink of Zen+, and the eventual 7nm shift and architectural update of Zen 2. AMD's Forest Norrod claims, in terms of IPC, Zen 3 will offer performance gains 'in line with what you would expect from a new architecture.'

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Considering Zen 2 was an evolutionary improvements over the original Zen architecture and brought an IPC increase of 15%, and with Zen 3 slated to be a totally new architecture, a chance does exist that Zen 3's IPC increase could be a fair number above the 15% mark. A rumor was circling around indicating AMD was considering the option to enable Zen 3 CPUs to utilize the SMT-4 function, but AMD has confirmed this to be false, as well as AMD's use of the 'tick-tock' process model. In an interview with Anandtech, Mark Papermaster made the following statement.

What I will say is that we're not on a tick-tock model. What we're doing is looking at each generation of CPU and marrying the best process variant that's out there with the right set of IPC improvements, memory hierarchy, and all the things that we can put in there. We are committed to staying on the best possible pace of improvements each generation that we can. This is a formula that's working well for AMD.

AMD Zen Roadmap

Vermeer & Renoir - Mainstream AM4 Desktop

AMD's upcoming desktop processors are referred to as Vermeer and Renoir internally, with Vermeer being the direct successor to Matisse, AMD's current lineup of Ryzen desktop CPUs, and Renoir being the replacement to existing Picasso APUs.

As of this moment, there's not much information available in regards to the 'Vermeer' desktop chips, and clock speeds are still a mystery, but there is a piece of information that AMD's Mark Papermaster gave to Tom's Hardware when asked if AMD would reach to 32 cores on the mainstream platform.

I don’t see in the mainstream space any imminent barrier, and here's why: It's just a catch-up time for software to leverage the multi-core approach, but we're over that hurdle, now more and more applications can take advantage of multi-core and multi-threading.

In the near term, I don’t see a saturation point for cores. You have to be very thoughtful when you add cores because you don’t want to add it before the application can take advantage of it. As long as you keep that balance, I think we'll continue to see that trend.

AMD AM4 Socket

As for Renoir, the upcoming family of APUs are expected to follow the traditional monolithic design that AMD's existing and previous APUs going back as far as Llano in 2011 have opted to utilize, and will not progress to the chiplet model as seen on Zen 2 CPUs. Renoir APUs may contain Zen 2 CPU cores and an updated variant of the Vega iGPU found within Raven Ridge and Picasso but will implement improved display and multimedia engines found within Navi.

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Genesis Peak & Milan - HEDT & Server/Datacenter

Similarly to Zen 2, both Genesis Peak, the codename for 4th Generation Ryzen Threadripper and Milan, codename for 3rd Generation EPYC, will be built from the basis of Zen 3/Vermeer chiplets. As for Genesis Peak and Milan, AMD will integrate an updated version of Infinity Fabric, the primary method of data transport between chiplets.

AMD is expected to unveil their Zen 3 microarchitecture at CES 2020 (Image Credits: ChinaTimes)

Improvements with Infinity Fabric, in comparison from Zen 1/Zen+ to Zen 2, resulted in significant performance gains with 3rd Generation Ryzen Threadripper, correcting the bandwidth bottleneck existing within 2nd Generation Ryzen Threadripper HEDT processors. Not only was this achievable with just the Infinity Fabric improvement, but with a centralized I/O die under the hood of 2nd Generation EPYC and 3rd Generation Ryzen Threadripper, latency between chiplets was significantly reduced.