AMD EPYC Milan-X Server CPUs Leak Out, Up To 64 Zen 3 Cores & Possibly 3D V-Cache Stacks

Hassan Mujtaba
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AMD's next-generation EPYC Milan-X CPUs which will feature 3D Chiplet packaging has leaked out by Momomo_US. The lineup will serve as an intermediary solution before the Zen 4 powered EPYC Genoa lineup arrives later in 2022-2023.

AMD's EPYC Milan-X Server CPU SKUs Leak Out, Up To 64 Cores With 3D V-Cache Technology?

AMD has so far confirmed that it is bringing 3D V-Cache chip stacking technology to its Zen 3 core architecture. The technology would first be introduced on next-generation Ryzen Desktop CPUs & from the looks of it, another major product in the works with 3D V-Cache is Milan-X. AMD Milan-X has been known for a while and will be similar to existing Milan EPYC 7003 CPUs except they'll get major changes in the form of chiplet stacking.

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Following are the AMD EPYC 7003X Milan-X SKUs that were leaked:

  • EPYC 7773X 64 Core (100-000000504)
  • EPYC 7573X 32 Core (100-000000506)
  • EPYC 7473X 24 Core (100-000000507)
  • EPYC 7373X 16 Core (100-000000508)

Interestingly, all four SKUs listed here retain the same core counts as current variants so we aren't going to see CCD upon CCD level stacking so soon. The CCDs retain their integral cache count but will get a boost from the added SRAM cache through chiplet stacking.

Now what we know about the 3D V-Cache technology is that it is achieved through the use of Micro Bump (3D) & several TSV interconnects. The interconnect uses a brand new hydrophilic Dielectric-Dielectric Bonding with Direct CU-CU bonding which was designed and co-optimized in partnership with TSMC. The two individual silicons (chiplets) are bonded together using this technology. The 3D technology features 9 Micron Pitch bonds.

A single 3D V-Cache stack would incorporate 64 MB of L3 cache that sits on top of the TSV's already featured on existing Zen 3 CCD's. The cache will add upon the existing 32 MB of L3 cache for a total of 96 MB per CCD. AMD also stated that the V-Cache stack can go up to 8-hi which means a single CCD can technically offer up to 512 MB of L3 cache in addition to the 32 MB cache per Zen 3 CCD. So with a 64 MB of L3 cache, you can technically get up to 768 MB of L3 cache (8 3D V-Cache CCD stacks = 512 MB) which will be a mammoth increase in cache size.

3D V-Cache could just be one aspect of the EPYC Milan-X lineup. AMD might introduce faster clocks as 7nm continues to mature and we can see much faster performance from these stacked chips. It is also interesting that the OPN codes for these processors are ready which means that a launch by late 2022 is highly likely which would mean Milan-X might be the first chip to introduce 3D V-Cache.

AMD EPYC CPU Families:

Family BrandingEPYC 7007?EPYC 7006?EPYC 7004?EPYC 7005?EPYC 7004?EPYC 7004?EPYC 7003X?EPYC 7003EPYC 7002EPYC 7001
Family Launch2025+2024-2025?20232023202320222022202120192017
CPU ArchitectureZen 6?Zen 5Zen 4Zen 4CZen 4 V-CacheZen 4Zen 3Zen 3Zen 2Zen 1
Process NodeTBD3nm TSMC?5nm TSMC4nm TSMC5nm TSMC5nm TSMC7nm TSMC7nm TSMC7nm TSMC14nm GloFo
SocketTBDLGA 6096 (SP5)
LGA 4844LGA 6096LGA 6096LGA 6096LGA 4094LGA 4094LGA 4094LGA 4094
Max Core Count384?25664128969664646432
Max Thread Count768?51212825619219212812812864
Max L3 CacheTBDTBD256 MB?TBD1152 MB?384 MB?768 MB?256 MB256 MB64 MB
Chiplet DesignTBDTBD8 CCD's (1CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD8 CCD's with 3D V-Cache (1 CCX per CCD) + 1 IOD8 CCD's (1 CCX per CCD) + 1 IOD8 CCD's (2 CCX's per CCD) + 1 IOD4 CCD's (2 CCX's per CCD)
Memory SupportTBDDDR5-6000?DDR5-5200DDR5-5600?DDR5-5200DDR5-5200DDR4-3200DDR4-3200DDR4-3200DDR4-2666
Memory ChannelsTBD12 Channel (SP5)
6-Channel (SP6)
6-Channel12 Channel12 Channel12 Channel8 Channel8 Channel8 Channel8 Channel
PCIe Gen SupportTBDTBD96 Gen 5160 Gen 5160 Gen 5160 Gen 5128 Gen 4128 Gen 4128 Gen 464 Gen 3
TDP RangeTBD480W (cTDP 600W)70-225W320W (cTDP 400W)200W (cTDP 400W)200W (cTDP 400W)280W280W280W200W
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