After the huge dump of information that we got for AMD's next-generation EPYC Genoa Zen 4 CPU lineup yesterday, another rumor has popped up which states that AMD is going to feature two new technologies on Genoa that could pretty much destroy whatever hope Intel had left for its Sapphire Rapids & even next-generation Xeon lineups.
AMD EPYC Genoa CPUs Featuring Zen 4 Cores Rumored To Be Equipped With AVX3-512 & BFLOAT16 Instructions
According to an alleged slide posted on Chiphell Forums (via HXL), it is reported that AMD's Zen 4 core architecture for EPYC Genoa CPUs would allow for more than 64 cores per socket, 2 threads per core, and in up to 2 socket configurations. This is pretty much a reiteration of what was leaked out yesterday.
But what's next is quite interesting. It is stated that AMD's Zen 4 core architecture will feature 57-bit virtual and 52-bit physical addressing. The Zen 4 core architecture will also feature two new ISA's & those include AVX3-512, BFLOAT16, and a few other extensions that have not been stated. If AMD is definitely incorporating AVX 512 instructions on its next-generation lineup, which seems to be the case since ExecutableFix also validates this claim, AMD might get a significant advantage over Intel's Sapphire Rapids lineup.
The BFLOAT16 instruction set was also first featured on the Cooper Lake Xeon lineup from Intel and AMD is all set to introduce it for the EPYC platform too. Having AVX 512 and BFLOAT16 could take away all the advantages that Intel had. In mainstream HPC and datacenter benchmarks, AMD was cruising way ahead of Intel with the only saving grace for Intel being the few AVX-512 and AI accelerated workloads. AMD has the same level of ISA as Intel could just crush the Xeon lineup for ages to come. With that said, AVX-512 hardware does require a lot more power to run and that's one reason why we saw a huge increase in TDP for the upcoming lineup with TDPs of up to 400W being rumored.
Now, AMD is also giving it's EPYC Genoa lineup more cores and a brand new platform. The slide claims that there have been design and manufacturing improvements to performance & efficiency so we might be looking at some huge performance numbers for Genoa.
The main competitor of AMD's EPYC Genoa lineup would be Intel's Sapphire Rapids Xeon family which is expected to launch in 2022 too with PCIe Gen 5 and DDR5 memory support. The lineup was recently rumored to not get a volume ramp until 2023 which you can read more about over here. Overall, AMD's Genoa lineup seems to be in great form after this leak and could be a major disruption for the server segment if AMD plays its cards right till Genoa's launch.
AMD EPYC CPU Families:
| Family Name | AMD EPYC Verano | AMD EPYC Venice | AMD EPYC Turin-X | AMD EPYC Turin-Dense | AMD EPYC Turin | AMD EPYC Siena | AMD EPYC Bergamo | AMD EPYC Genoa-X | AMD EPYC Genoa | AMD EPYC Milan-X | AMD EPYC Milan | AMD EPYC Rome | AMD EPYC Naples |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Family Branding | EPYC 9007 | EPYC 9006 | EPYC 9005 | EPYC 9005 | EPYC 9005 | EPYC 8004 | EPYC 9004 | EPYC 9004 | EPYC 9004 | EPYC 7004 | EPYC 7003 | EPYC 7002 | EPYC 7001 |
| Family Launch | 2027 | 2026 | 2025 | 2025 | 2024 | 2023 | 2023 | 2023 | 2022 | 2022 | 2021 | 2019 | 2017 |
| CPU Architecture | Zen 7 | Zen 6 | Zen 5 | Zen 5C | Zen 5 | Zen 4 | Zen 4C | Zen 4 V-Cache | Zen 4 | Zen 3 | Zen 3 | Zen 2 | Zen 1 |
| Process Node | TBD | 2nm TSMC | 4nm TSMC | 3nm TSMC | 4nm TSMC | 5nm TSMC | 4nm TSMC | 5nm TSMC | 5nm TSMC | 7nm TSMC | 7nm TSMC | 7nm TSMC | 14nm GloFo |
| Platform Name | SP7 | SP7 | SP5 | SP5 | SP5 | SP6 | SP5 | SP5 | SP5 | SP3 | SP3 | SP3 | SP3 |
| Socket | TBD | TBD | LGA 6096 (SP5) | LGA 6096 (SP5) | LGA 6096 | LGA 4844 | LGA 6096 | LGA 6096 | LGA 6096 | LGA 4094 | LGA 4094 | LGA 4094 | LGA 4094 |
| Max Core Count | TBD | 96 | 128 | 192 | 128 | 64 | 128 | 96 | 96 | 64 | 64 | 64 | 32 |
| Max Thread Count | TBD | 192 | 256 | 384 | 256 | 128 | 256 | 192 | 192 | 128 | 128 | 128 | 64 |
| Max L3 Cache | TBD | TBD | 1536 MB | 384 MB | 384 MB | 256 MB | 256 MB | 1152 MB | 384 MB | 768 MB | 256 MB | 256 MB | 64 MB |
| Chiplet Design | TBD | 8 CCD's (1 CCX per CCD) + 2 IOD? | 16 CCD's (1CCX per CCD) + 1 IOD | 12 CCD's (1CCX per CCD) + 1 IOD | 16 CCD's (1CCX per CCD) + 1 IOD | 8 CCD's (1CCX per CCD) + 1 IOD | 12 CCD's (1 CCX per CCD) + 1 IOD | 12 CCD's (1 CCX per CCD) + 1 IOD | 12 CCD's (1 CCX per CCD) + 1 IOD | 8 CCD's (1 CCX per CCD) + 1 IOD | 8 CCD's (1 CCX per CCD) + 1 IOD | 8 CCD's (2 CCX's per CCD) + 1 IOD | 4 CCD's (2 CCX's per CCD) |
| Memory Support | TBD | DDR5-12800 | DDR5-6000? | DDR5-6400 | DDR5-6400 | DDR5-5200 | DDR5-5600 | DDR5-4800 | DDR5-4800 | DDR4-3200 | DDR4-3200 | DDR4-3200 | DDR4-2666 |
| Memory Channels | TBD | 16-Channel (SP7) | 12 Channel (SP5) | 12 Channel | 12 Channel | 6-Channel | 12 Channel | 12 Channel | 12 Channel | 8 Channel | 8 Channel | 8 Channel | 8 Channel |
| PCIe Gen Support | TBD | 128-192 PCIe Gen 6 | TBD | 128 PCIe Gen 5 | 128 PCIe Gen 5 | 96 Gen 5 | 128 Gen 5 | 128 Gen 5 | 128 Gen 5 | 128 Gen 4 | 128 Gen 4 | 128 Gen 4 | 64 Gen 3 |
| TDP (Max) | TBD | ~600W | 500W (cTDP 600W) | 500W (cTDP 450-500W) | 400W (cDP 320-400W) | 70-225W | 320W (cTDP 400W) | 400W | 400W | 280W | 280W | 280W | 200W |
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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