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AMD EPYC Server Roadmap Leaks Out: EPYC Genoa-X With Zen 4 & 3D-V-Cache in 1H 2023, Genoa, Bergamo & Turin With SP6 Support

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An alleged roadmap of AMD's next-gen EPYC Server CPUs and Platform has been leaked out by AdoredTV. The roadmap lists upcoming server CPUs Genoa, Bergamo, Genoa-X, and Turin, along with a new platform known as SP6.

AMD's Alleged EPYC Server CPU & Platform Roadmap Spills The Beans on Genoa-X, Turin, and SP6

We cannot confirm the validity of the roadmap slides hence this post is to be treated as a rumor but most of the details were also reported previously by other leakers so it's worth sharing. First up, there's the EPYC Server CPU roadmap for 2021-2023. The roadmap not only lists down EPYC server chips but also the respective platforms they are aimed at. AMD recently launched its final SP3 platform chips, the EPYC 7003X 'Milan-X' which are based on the Zen 3 core architecture with 3D V-Cache.

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AMD EPYC Server CPU and Platform roadmap has been leaked. (Image Credits: AdoredTV)

EPYC Zen 4(C) Expanded With Genoa, Bergamo, and Genoa-X

Moving on, AMD wants to focus on the SP5 platform which is based around the LGA 6096 socket and will feature at least two generations of processor lineups, Genoa and Bergamo. The AMD EPYC Genoa CPUs will feature up to 96 Zen 4 cores in 200-400W SKUs while Bergamo will feature a total of 128 Zen 4 cores in 320-400W SKUs. The SP5 platform is a high-end design that offers both 1P & 2P support, up to 12-Channel DDR5 memory, up to 160 PCIe Gen 5.0 lanes, and 64 Lanes for CXL V1.1+, and up to 12 PCIe Gen 3.0 lanes.

The same roadmap also mentions Genoa-X, something that was also mentioned by Moore's Law is Dead in his video yesterday. The Genoa-X CPUs are expected to hit production by end of Q3 / early Q1 2023 and will launch around mid of 2023. They will feature a similar design methodology as the Milan-X chips with 3D V-Cache as 'Large L3' is a highlighted feature of the lineup. So in total, SP5 will end up with three EPYC families.

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At the same time, AMD is expected to introduce a new platform known as SP6 which will be a more TCO-optimized offering for low-end servers. It will be a 1P solution, offering 6-channel memory, 96 PCIe Gen 5.0 lanes, 48 lanes for CXL V1.1+, and 8 PCIe Gen 3.0 lanes. The platform will feature Zen 4 EPYC CPUs but only the entry-level solutions with up to 32 Zen 4 and up to 64 Zen 4C cores. Their TDPs will range between 70-225W. So it looks like the SP6 platform is designed to support the entry level variants of EPYC Genoa, Bergamo, and even Turin CPUs. It will focus on Density & Perf/Watt optimizations for Edge / Telecommunication segment leadership.

The roadmap confirms next-gen products such as EPYC Genoa-X, Turin for SP5 and SP6 platforms. (Image Credits: AdoredTV)

In documentation discovered by @Olrak (via Anandtech Forums), it looks like the SP6 socket is vastly similar to the existing SP3 socket so the packaging layout of the SP6 chips will be similar compared to existing EPYC CPUs too. They won't use the full 12-die layout as Bergamo does but rather stick to an 8-die layout as the existing parts. While the socket looks the same, the internal pin layout has been modified to LGA 4844 vs LGA 4096 (on SP3 sockets). Other measurements are the same at 58.5 x 75.4.

Most of these products are expected to hit the market in the second half of 2022 and the first half of 2024. We can expect a formal announcement of the new roadmap by AMD soon and a possible unveil during the Computex 2022 event which is slated in a few week's time.

AMD EPYC CPU Families:

Family NameAMD EPYC NaplesAMD EPYC RomeAMD EPYC MilanAMD EPYC Milan-XAMD EPYC GenoaAMD EPYC BergamoAMD EPYC TurinAMD EPYC Venice
Family BrandingEPYC 7001EPYC 7002EPYC 7003EPYC 7003X?EPYC 7004?EPYC 7005?EPYC 7006?EPYC 7007?
Family Launch2017201920212022202220232024-2025?2025+
CPU ArchitectureZen 1Zen 2Zen 3Zen 3Zen 4Zen 4CZen 5Zen 6?
Process Node14nm GloFo7nm TSMC7nm TSMC7nm TSMC5nm TSMC5nm TSMC3nm TSMC?TBD
Platform NameSP3SP3SP3SP3SP5 / SP6SP5 / SP6SP5 / SP6TBD
SocketLGA 4094LGA 4094LGA 4094LGA 4094LGA 6096 (SP5)
LGA XXXX (SP6)
LGA 6096 (SP5)
LGA XXXX (SP6)
LGA 6096 (SP5)
LGA XXXX (SP6)
TBD
Max Core Count3264646496128256384?
Max Thread Count64128128128192256512768?
Max L3 Cache64 MB256 MB256 MB768 MB?384 MB?TBDTBDTBD
Chiplet Design4 CCD's (2 CCX's per CCD)8 CCD's (2 CCX's per CCD) + 1 IOD8 CCD's (1 CCX per CCD) + 1 IOD8 CCD's with 3D V-Cache (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IODTBDTBD
Memory SupportDDR4-2666DDR4-3200DDR4-3200DDR4-3200DDR5-5200DDR5-5600?DDR5-6000?TBD
Memory Channels8 Channel8 Channel8 Channel8 Channel12 Channel (SP5)
6-Channel (SP6)
12 Channel (SP5)
6-Channel (SP6)
12 Channel (SP5)
6-Channel (SP6)
TBD
PCIe Gen Support64 Gen 3128 Gen 4128 Gen 4128 Gen 4160 Gen 5 (SP5)
96 Gen 5 (SP6)
160 Gen 5 (SP5)
96 Gen 5 (SP6)
TBDTBD
TDP Range200W280W280W280W200W (cTDP 400W) SP5
70-225W SP6
320W (cTDP 400W) SP5
70-225W SP6
480W (cTDP 600W)TBD

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