AMD EPYC Server Roadmap Leaks Out: EPYC Genoa-X With Zen 4 & 3D-V-Cache in 1H 2023, Genoa, Bergamo & Turin With SP6 Support

An alleged roadmap of AMD's next-gen EPYC Server CPUs and Platform has been leaked out by AdoredTV. The roadmap lists upcoming server CPUs Genoa, Bergamo, Genoa-X, and Turin, along with a new platform known as SP6.

AMD's Alleged EPYC Server CPU & Platform Roadmap Spills The Beans on Genoa-X, Turin, and SP6

We cannot confirm the validity of the roadmap slides hence this post is to be treated as a rumor but most of the details were also reported previously by other leakers so it's worth sharing. First up, there's the EPYC Server CPU roadmap for 2021-2023. The roadmap not only lists down EPYC server chips but also the respective platforms they are aimed at. AMD recently launched its final SP3 platform chips, the EPYC 7003X 'Milan-X' which are based on the Zen 3 core architecture with 3D V-Cache.

EPYC Zen 4(C) Expanded With Genoa, Bergamo, and Genoa-X

Moving on, AMD wants to focus on the SP5 platform which is based around the LGA 6096 socket and will feature at least two generations of processor lineups, Genoa and Bergamo. The AMD EPYC Genoa CPUs will feature up to 96 Zen 4 cores in 200-400W SKUs while Bergamo will feature a total of 128 Zen 4 cores in 320-400W SKUs. The SP5 platform is a high-end design that offers both 1P & 2P support, up to 12-Channel DDR5 memory, up to 160 PCIe Gen 5.0 lanes, and 64 Lanes for CXL V1.1+, and up to 12 PCIe Gen 3.0 lanes.

The same roadmap also mentions Genoa-X, something that was also mentioned by Moore's Law is Dead in his video yesterday. The Genoa-X CPUs are expected to hit production by end of Q3 / early Q1 2023 and will launch around mid of 2023. They will feature a similar design methodology as the Milan-X chips with 3D V-Cache as 'Large L3' is a highlighted feature of the lineup. So in total, SP5 will end up with three EPYC families.

What's SP6? A Cost-Optimized Version of SP5 For Edge Servers

At the same time, AMD is expected to introduce a new platform known as SP6 which will be a more TCO-optimized offering for low-end servers. It will be a 1P solution, offering 6-channel memory, 96 PCIe Gen 5.0 lanes, 48 lanes for CXL V1.1+, and 8 PCIe Gen 3.0 lanes. The platform will feature Zen 4 EPYC CPUs but only the entry-level solutions with up to 32 Zen 4 and up to 64 Zen 4C cores. Their TDPs will range between 70-225W. So it looks like the SP6 platform is designed to support the entry level variants of EPYC Genoa, Bergamo, and even Turin CPUs. It will focus on Density & Perf/Watt optimizations for Edge / Telecommunication segment leadership.

In documentation discovered by @Olrak (via Anandtech Forums), it looks like the SP6 socket is vastly similar to the existing SP3 socket so the packaging layout of the SP6 chips will be similar compared to existing EPYC CPUs too. They won't use the full 12-die layout as Bergamo does but rather stick to an 8-die layout as the existing parts. While the socket looks the same, the internal pin layout has been modified to LGA 4844 vs LGA 4096 (on SP3 sockets). Other measurements are the same at 58.5 x 75.4.

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Most of these products are expected to hit the market in the second half of 2022 and the first half of 2024. We can expect a formal announcement of the new roadmap by AMD soon and a possible unveil during the Computex 2022 event which is slated in a few week's time.

AMD EPYC CPU Families:

Family Name	AMD EPYC Verano	AMD EPYC Venice	AMD EPYC Turin-X	AMD EPYC Turin-Dense	AMD EPYC Turin	AMD EPYC Siena	AMD EPYC Bergamo	AMD EPYC Genoa-X	AMD EPYC Genoa	AMD EPYC Milan-X	AMD EPYC Milan	AMD EPYC Rome	AMD EPYC Naples
Family Branding	EPYC 9007	EPYC 9006	EPYC 9005	EPYC 9005	EPYC 9005	EPYC 8004	EPYC 9004	EPYC 9004	EPYC 9004	EPYC 7004	EPYC 7003	EPYC 7002	EPYC 7001
Family Launch	2027	2026	2025	2025	2024	2023	2023	2023	2022	2022	2021	2019	2017
CPU Architecture	Zen 7	Zen 6	Zen 5	Zen 5C	Zen 5	Zen 4	Zen 4C	Zen 4 V-Cache	Zen 4	Zen 3	Zen 3	Zen 2	Zen 1
Process Node	TBD	2nm TSMC	4nm TSMC	3nm TSMC	4nm TSMC	5nm TSMC	4nm TSMC	5nm TSMC	5nm TSMC	7nm TSMC	7nm TSMC	7nm TSMC	14nm GloFo
Platform Name	SP7	SP7	SP5	SP5	SP5	SP6	SP5	SP5	SP5	SP3	SP3	SP3	SP3
Socket	TBD	TBD	LGA 6096 (SP5)	LGA 6096 (SP5)	LGA 6096	LGA 4844	LGA 6096	LGA 6096	LGA 6096	LGA 4094	LGA 4094	LGA 4094	LGA 4094
Max Core Count	TBD	96	128	192	128	64	128	96	96	64	64	64	32
Max Thread Count	TBD	192	256	384	256	128	256	192	192	128	128	128	64
Max L3 Cache	TBD	TBD	1536 MB	384 MB	384 MB	256 MB	256 MB	1152 MB	384 MB	768 MB	256 MB	256 MB	64 MB
Chiplet Design	TBD	8 CCD's (1 CCX per CCD) + 2 IOD?	16 CCD's (1CCX per CCD) + 1 IOD	12 CCD's (1CCX per CCD) + 1 IOD	16 CCD's (1CCX per CCD) + 1 IOD	8 CCD's (1CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (2 CCX's per CCD) + 1 IOD	4 CCD's (2 CCX's per CCD)
Memory Support	TBD	DDR5-12800	DDR5-6000?	DDR5-6400	DDR5-6400	DDR5-5200	DDR5-5600	DDR5-4800	DDR5-4800	DDR4-3200	DDR4-3200	DDR4-3200	DDR4-2666
Memory Channels	TBD	16-Channel (SP7)	12 Channel (SP5)	12 Channel	12 Channel	6-Channel	12 Channel	12 Channel	12 Channel	8 Channel	8 Channel	8 Channel	8 Channel
PCIe Gen Support	TBD	128-192 PCIe Gen 6	TBD	128 PCIe Gen 5	128 PCIe Gen 5	96 Gen 5	128 Gen 5	128 Gen 5	128 Gen 5	128 Gen 4	128 Gen 4	128 Gen 4	64 Gen 3
TDP (Max)	TBD	~600W	500W (cTDP 600W)	500W (cTDP 450-500W)	400W (cDP 320-400W)	70-225W	320W (cTDP 400W)	400W	400W	280W	280W	280W	200W

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