3D X-DRAM Hits Proof-of-Concept, HBM-Replacement with 10x Density vs Traditional DRAM & High-Yield Memory Design

Think of DRAM, but in a NAND-like structure, that's the basic concept of 3D X-DRAM, a revolution for the memory markets, bringing higher densities for AI.

3D X-DRAM Is Now Closer To Reality, An HBM-Replacement That Offers Higher Densities For AI

In 2023, US-based NEO Semiconductor announced its brand new project called 3D X-DRAM, which was going to address the DRAM capacity bottleneck by leveraging a 3D NAND-like architecture. The company also unveiled two 3D X-DRAM cells, which will be integrated into memory solutions based on 3D X-DRAM.

These include 1T1C and 3T0C DRAM cells, offering up to 512Gb, a 10x improvement in density versus traditional DRAM, while being cost-effective and ready for high-yield production. Each 3D X-DRAM variant is designed for various purposes. For example, 1T1C is compatible with mainstream DRAM & HBM roadmaps, offering high-density DRAM, while 3T0C is ideal for AI workloads.

• 1T1C (one transistor, one capacitor) – The core solution for high-density DRAM, fully compatible with mainstream DRAM and HBM roadmaps.
• 3T0C (three transistor, zero capacitor) – Optimized for current-sensing operations, ideal for AI and in-memory computing.
• 1T0C (one transistor, zero capacitor) – A floating-body cell structure suitable for high-density DRAM, in-memory computing, hybrid memory, and logic architectures.

The main features of this announcement included:

• Unmatched Retention and Efficiency – Thanks to IGZO channel technology, 1T1C and 3T0C cell simulations demonstrate retention times of up to 450 seconds, dramatically reducing refresh power.
• Verified by Simulation – TCAD (Technology Computer-Aided Design) simulations confirm fast 10-nanosecond read/write speeds and over 450-second retention time.
• Manufacturing-Friendly – Uses a modified 3D NAND process, with minimal changes, enabling full scalability and rapid integration into existing DRAM manufacturing lines.
• Ultra-High Bandwidth – Employs unique array architectures for hybrid bonding to significantly enhance memory bandwidth while reducing power consumption.
• High Performance for Advanced Workloads – Designed for AI, edge computing, and in-memory processing, with reliable high-speed access and reduced energy consumption.

An advantage that DRAM has over HBM is that High-Bandwidth Memory, while the leading choice for AI and HPC segments, is hard to produce, expensive, and requires lots of testing/verification before it can be deployed on server chips. In contrast, DRAM is easy to produce and doesn't require as many checks. The 3D X-DRAM also deploys a monolithic-like architecture within a single die rather than stacking multiple DRAM dies on top of each other as HBM does.

Today, NEO Semiconductor has demonstrated the 3D X-DRAM Proof-of-Concept and also secured investments to further advance the project. With the POC test chips, the company has demonstrated that 3D X-DRAM can be manufactured using existing 3D NAND infrastructure, adding multiple layers of DRAM instead of a stack like HBM memory.

The first test results of the POC test chips are as follows:

• Read/write latency: <10 ns
• Data retention: >1 second at 85°C (15× better than the 64 ms JEDEC standard)
• Bit-line disturbance: >1 second at 85°C
• Word-line disturbance: >1 second at 85°C
• Endurance: >10¹⁴ cycles

As memory demand grows in the AI and HPC segments, advanced DRAM solutions will become a necessity. Intel is also preparing a similar DRAM architecture called ZAM (Z-Angle Memory) for this purpose. As of right now, neither of the two DRAM architectures is in production, far from it; however, given their progress and continued investments by major firms, we will be able to see these technologies power the server landscape within this decade.

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