Work on Next-Gen HBM5 & HBM6 Memory Is Already Underway, New Wide TC Bonders Ready

HBM memory will see a big upgrade with next-gen HBM5 and HBM6 standards, which are already being developed with new TC Bonders.

Semiconductor Firm, Hanmi, Showcases First Wide TC Bonders Designed For Next-Gen HBM5 and HBM6 Memory

NVIDIA and AMD are both going to launch their next-gen AI accelerators this year with HBM4 memory. These include the Vera Rubin and Instinct MI450 series products. But given the pace at which the AI tech industry is moving, work is already underway on the next-gen standards, namely HBM5 and HBM6.

A report from Korean outlet, Heraldcorp, reveals that the first Wide TC Bonder, which will be used in the production of the next-gen memory standards are all set to be revealed at the 2026 Semicon in Korea. The Wide TC Bonder is an equipment which will be used as as alterative to the Hybrid Bonder (HB) for the mass production of HBM memory.

What makes Wide TC Bonder interesting is the fact that the Hybrid Bonder equipment faced technical difficulties and had to be delayed. Meanwhile, Wide TC Bonder not only has the ability to increase HBM production yield for existing and future standards such as HBM4, HBM4E, HBM5, and HBM6, but it also provides improved quality and completeness by applying advanced precision bonding technology.

Another highlight of the Wide TC Bonder is that it has a technology called fluxless bonding, which reduces the oxide layer on the chip's surface without flux, increasing its bond strength while reducing overall HBM thickness.

HBM5 Targets NVIDIA Feynman With An On-Shelf Release Scheduled For 2029

HBM5 seems to stick to the 8 Gbps data rate for the Non-e variant, but drives up the IO lanes to 4096 bits. The bandwidth also increases to 4 TB/s per stack and will come with 16-Hi stacks as the baseline. With 40 Gb DRAM dies, HBM5 will scale to 80 GB capacity per stack, and the per-stack power is expected to hit 100W.

Main features of the HBM5 memory standard include:

• Data Rate: 8 Gbps
• Number of I/Os: 4096
• Total Bandwidth: 4.0 TB/s
• Number of die stacks: 16-Hi
• Capacity per die: 40 Gb
• Capacity per HBM: 80 GB
• Package Power per HBM: 100W
• Packaging Method: Microbump (MR-MUF)
• Cooling Method: Immersion Cooling, Thermal Via (TTV), Thermal Bonding
• Dedicated decoupling capacitor chip die stack
• Custom HBM Base Die w/ 3D NMC-HBM & Stacked Cache
• LPDDR+CXL in Base Die
• NVIDIA Feynman & Instinct MI500 Platforms

HBM6 For Post-Feynman GPU Architecture - Massive Power, Massive Capacities, Lots of Bandwidth

The bandwidth doubles to 8 TB/s, and we're pushing for 48 Gb capacities per DRAM die. Another big change over HBM5 is that this should be the first time we get to see HBM stacking go beyond 16-Hi to 20-Hi, increasing the memory capacities to 96-120 GB per stack with a per-stack power of 120W. Both HBM5 and HBM6 are expected to feature Immersion Cooling solutions, with the latter going for a multi-tower HBM (Active/Hybrid) interpose architecture and additional features such as onboard Network Switch, Bridge Die, and Asymmetric TSV in the research phase.

Main features of the HBM6 memory standard include:

• Data Rate: 16 Gbps
• Number of I/Os: 4096
• Total Bandwidth: 8.0 TB/s
• Number of die stacks: 16/20-Hi
• Capacity per die: 48 Gb
• Capacity per HBM: 96/120 GB
• Package Power per HBM: 120W
• Packaging Method: Bump-less Cu-Cu Direct Bonding
• Cooling Method: Immersion Cooling
• Custom Multi-tower HBMs
• Active/Hybrid (Silicon+Glass) interposer
• Network Switch + Bridge Die

Currently, HBM4 is all set to entire mass production this year, and development of HBM5 and HBM6 is also prepped around this time. HBM5 and HBM6 memory standards will offer incremental speeds up & technology updates versus HBM4, which is already going to be way faster than anything we've seen before.

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