The Taiwan Semiconductor Manufacturing Company (TSMC) is expanding its supply chain for glass substrates as part of the first step of establishing a supply chain for the chip-on-panel-on-substrate (CoPoS) packaging technology, according to supply chain sources. The glass substrates will be used in the firm's advanced versions of the chip-on-wafer-on-substrate (CoWoS) packaging technology, and TSMC is working with Innolux and Ibiden as part of these efforts.
TSMC Gears Up For Glass Substrate Development By Sharing Plan With Suppliers
According to the details, the two companies that TSMC is in touch with are its suppliers for Ajinomoto Buildup Film (ABF) and panels. The goal of these discussions is to address issues such as heat management, signal transmission and warpage that could affect the performance of high-performance computing (HPC) chips in the future.
A key factor that has stimulated TSMC's interest in glass substrates is the package-warpage indicator, which measures the bending and twisting of components. Specifically, the report from DigiTimes suggests that the warpage indicator dropped by 16%, while other parameters, such as thermal expansion, resistance and inductance dropped by 19%, 27% and 42%, respectively. Yet, even though glass substrates have shown advantages, they are still some time away from mass production, as per the sources.
TSMC Plans To Initially Use Glass In CoWoS Technology, Say Sources
Yet, the sources add that the warpage figures mean that glass substrates can be suitable for high-end AI GPUs such as NVIDIA's Rubin and Blackwell chips. The improvements in thermal efficiency allow glass to better mimic silicon's performance since silicon's thermal figures are quite different from those of organic substrates.
TSMC's test sample was a substrate with a glass core, which did not experience warpage or peeling to affect yield. The sources add that another major challenge for glass substrates is conductivity. Since glass is not a conductor, manufacturers have to insert vertical conductive paths called 'vias' in order to facilitate the transfer of current.
The report follows comments by a TSMC executive at the firm's European Symposium, where he insisted that CoWoS will continue to remain the mainstay packaging technology for advanced AI chips. As reported by Tom's Hardware, TSMC's Kevin Zhang remarked that constraints such as geometric complexity meant that CoWoS remained the preferred option over the panel-level technology.
About the author: Ramish is a seasoned technology writer and editor with more than a decade of experience. He specializes in semiconductor fabrication and market analysis. With a background in finance and supply chain management - via his bachelors in Finance and a micromasters in supply chain management from MIT - Ramish combines financial rigor with deep industry insight to deliver accurate and authoritative coverage.
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