In its ‘Semiconductor Technology Roadmap 2026,’ The Institute of Semiconductor Engineers announced the forecast of silicon development for the next 15 years. Where Samsung only recently announced the world’s first 2nm GAA chipset, the Exynos 2600, by 2040, it is predicted that semiconductor circuits will reach 0.2nm, entering the angstrom (A) era. However, significant progress is required between now and more than a decade and a half from now, with numerous potholes and obstacles standing in the way of achieving sub-1nm wafers.
Additional predictions for semiconductor advancements include NAND flash layers increasing to 2,000 layers from 321, along with AI semiconductors performing tens of trillions of operations per second
A report from ETNews states that the purpose of the roadmap is to ‘contribute to strengthening long-term semiconductor technology and industry competitiveness, activating academic research, and establishing human resource development strategies.’ The roadmap presented by the Institute of Semiconductor Engineers is for nine core technologies: semiconductor devices and processes, artificial intelligence semiconductors, optical connection semiconductors, wireless connection semiconductor sensors, wired connection semiconductors, PI M, packaging, and Quantum computing.
The lowest lithography current belongs to Samsung’s 2nm Gate-All-Around (GAA) technology, but the Korean giant has reportedly planned better variants of this manufacturing process. For instance, it has completed the basic design of its second-generation 2nm GAA node and is reported to implement its SF2P+, which is the third-generation 2nm GAA technology, within two years. By 2040, it is estimated that the 0.2nm process will employ a generation transistor structure, CFET (Complementary Field Effect Transistor), and a monolithic 3D design.
Samsung, which is currently the leader in Korea for next-generation semiconductor manufacturing, is also said to have formed a team to begin research on 1nm chip development, with a mass production target set for 2029. These improvements are not only said to be applied to mobile SoCs, but also DRAM, whose memory circuit will shrink from 11nm to 6nm, and High-Bandwidth Memory will reportedly advance from 12 layers and 2TB/s bandwidth to 30 layers and 128TB/s bandwidth.
As for NAND, where SK hynix has developed 321-layer QLC technology, semiconductor advancements will allow for 2,000 layers of QLC NAND. Lastly, we have AI processors that can achieve 10 TOPS (trillion operations per second), but in a decade and a half, the report states that we could have chips that can generate 1,000 TOPS per second for learning and 100 TOPS for inference.
News Source: ETNews
About the author: Omar Sohail is a reporter and analyst for Wccftech's mobile section, specializing in the technology and business of the mobile industry. His expertise lies in the intricate hardware supply chain, covering developments in semiconductor manufacturing, chip lithography, and camera sensor technology.
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