By now, everyone and their grandmother is familiar with ASML, the sole provider of EUV (Extreme Ultraviolet) capable lithography machines in the world.
As hyperscalers continue to aggressively build out compute, we constantly discover new bottlenecks at almost every level of Jensen's five-layer AI cake, down to an insulating film supplied by, of all things, an MSG manufacturer. Yet for all the novel bottlenecks that crop up, there remains a perennial, critical constraint to AI build-out: the capacity of leading fabs to produce wafers on bleeding-edge process nodes.
In other words, this bottleneck is EUV capacity, as all sub-7 nm nodes require EUV lithography. On the foundry side, increasing EUV tool uptime and utilization can increase output, but only to a certain limit. With only a limited number of machines made each year - and foundries scrambling to secure allocations - the EUV bottleneck looks to be as relevant as ever, as we continue into the hyperscale era. ASML is naturally aware of this, and so historically has looked to High-NA (Numerical Aperture) as the next step for EUV.
This technology enables smaller features to be printed without multiple exposure passes, significantly reducing the complexity of continuing to scale down process nodes. Intel was one of the first (and most aggressive) adopters, and has found that going from 0.33 NA EUV (considered Low-NA) to 0.55 High-NA EUV can reduce exposures from 3 down to 1, with a similar reduction for the number of steps in the mask process.
ASML's High-NA Journey Is Rapidly Approaching HVM
The first shipment of a 0.55 NA lithography machine - specifically, the EXE:5000 - was in Q4 '23, with almost another year until the first wafer was exposed on it, in Q3 '24. This machine is capable of 110 WpH (wafers per hour), and its successor, the EXE:5200B, was first delivered to customers in Q4 '25, capable of 175 WpH (using the 1000W laser source revealed in 2025).
Production has also hit significant milestones, reaching 500k High-NA wafers in December '25. Although we've had to wait a long time for High NA to come to fruition, with foundries now deep into production qualification, it looks like HVM (High Volume Manufacturing) isn't far off.
"So summarizing, we see that the journey is towards HVM is progressing with very good momentum being built at customers by the 5,000 and 5200b results..."
— Chris De Ruiter, ASML (SPIE EUVL 2026)
Towards Hyper-NA
Beyond 0.55 High-NA, ASML has recently introduced the next step, Hyper-NA. Hyper-NA EUV is defined as > 0.75 NA, and will enable further downward scaling past the A7 node (expected to reach HVM around 2033). In order to keep single patterning feasible, a further increase in Numerical Aperture must be made by around the second half of the 2030s.
"So what this graph tells you that if you look at the prediction or the expectation of the shrink roadmap, and with the uncertainty indicated, then probably we need to make a next step by the second half of the next decennium."
— Jos Benschop, ASML (SPIE EUVL 2026)
Fortunately, Hyper-NA will not require drastically larger optics compared to High-NA. This enables ASML to reuse the High Performance Platform introduced with High-NA (machines named EXE:).
As the graph above illustrates, increasing NA allows for a reduction in the number of mask steps during the lithography process, which drives reduced energy consumption as well. Therefore, although Hyper-NA will undoubtedly drive tool costs up (just as High-NA has), eventually it will become affordable, driving the future of EUV and with it, the future of semiconductors.
Credits & Permissions
Figures and slides in this article are reproduced with special permission granted exclusively for this Wccftech.com article. Please do not reproduce or republish these images elsewhere without obtaining your own permission from the authors and SPIE.
Material from:
- C. De Ruiter et al., “High-NA EUV for high volume manufacturing,” Proc. SPIE 13979, Optical and EUV Nanolithography XXXIX (2026)
- J. Benschop et al., “Hyper-NA at 13.5nm: a natural next step to extend single-exposure EUV lithography,” Proc. SPIE 13979, Optical and EUV Nanolithography XXXIX (2026)
The author would like to thank SPIE and ASML for their kind permission to reproduce this material, and especially the authors for their support.
About the author: Rayan is an aspiring Computer Engineer, currently pursuing his undergraduate studies. He built his first computer in the pandemic, and has been hooked on the hobby ever since. He brings a unique blend of academic knowledge and technical know-how to his articles, which include everything from detailed instructional guides to performance comparisons in wccftech hardware section. When not stressing out over finals or writing articles, you can find him reading fantasy books or hitting the gym.
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