Rambus has detailed its next-gen HBM4 Memory Controller which will allow significant uplifts over existing HBM3 and HBM3E solutions.
HBM4 Will Begin the next chapter of AI & Data Center Evolution, Delivering Faster Memory Speeds & Higher Capacities Per Stack
As JEDEC moves towards the finalization of the HBM4 memory spec, we have our first details of what the next-generation solution would offer. Aimed primarily at the AI and Data Center market, the HBM4 memory solution is going to continue to expand the capabilities of existing HBM DRAM design.
Starting with the details, Rambus announced its HBM4 memory controller which is going to offer over 6.4 Gb/s speeds per pin which should be faster than the first generation of HBM3 solution while offering more bandwidth than HBM3E solutions using the same 16-Hi stack and 64 GB max capacity design. The starting bandwidth for HBM4 is rated at 1638 GB/s which is 33% higher than HBM3E and 2x higher than HBM3.
Currently, HBM3E solutions operate at up to 9.6 Gb/s speeds with up to 1.229 TB/s of bandwidth per stack. With HBM4, the memory solution is going to offer up to 10 Gb/s speeds and up to 2.56 GB/s of bandwidth per HBM interface. That will mark more than a 2x increase over HBM3E but the full capabilities of HBM4 memory won't be seen for a while and only become accessible once yields get better. Other features of the HBM4 memory solution include ECC, RMW (Read-Modify-Write), Error Scrubbing, etc.
As of right now, SK Hynix has reportedly begun mass production of its 12-layer HBM3E memory with up to 36 GB capacities and 9.6 Gbps speeds while its next-gen HBM4 memory is expected to tape out this month. Meanwhile, Samsung is expected to go into mass production for its HBM4 memory by the end of 2025 with tape out expected this quarter.
As of right now, NVIDIA's Rubin GPUs which are expected to arrive in 2026 are going to be the first AI platform to feature HBM4 memory support while Instinct MI400 is also expected to utilize the next-gen design however AMD hasn't confirmed that yet.
HBM Memory Specifications Comparison
| DRAM | HBM1 | HBM2 | HBM2e | HBM3 | HBM3E | HBMNext (HBM4) |
|---|---|---|---|---|---|---|
| I/O (Bus Interface) | 1024 | 1024 | 1024 | 1024 | 1024-2048 | 1024-2048 |
| Prefetch (I/O) | 2 | 2 | 2 | 2 | 2 | 2 |
| Maximum Bandwidth | 128 GB/s | 256 GB/s | 460.8 GB/s | 819.2 GB/s | 1.2 TB/s | 1.5 - 2.56 TB/s |
| DRAM ICs Per Stack | 4 | 8 | 8 | 12 | 8-16 | 8-16 |
| Maximum Capacity | 4 GB | 8 GB | 16 GB | 24 GB | 24 - 36 GB | 36-64 GB |
| tRC | 48ns | 45ns | 45ns | TBA | TBA | TBA |
| tCCD | 2ns (=1tCK) | 2ns (=1tCK) | 2ns (=1tCK) | TBA | TBA | TBA |
| VPP | External VPP | External VPP | External VPP | External VPP | External VPP | TBA |
| VDD | 1.2V | 1.2V | 1.2V | TBA | TBA | TBA |
| Command Input | Dual Command | Dual Command | Dual Command | Dual Command | Dual Command | Dual Command |
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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