Qualcomm’s HBC Stacks Compute Beneath DRAM To Smash The AI Memory Wall, Claiming 6x The Bandwidth Per Watt Of HBM

Jun 24, 2026 at 05:15pm EDT
A layered chip with gold-colored elements is shown above the text '200x capacity per watt vs. SRAM*'.

Qualcomm is unveiling its breakthrough for the AI data center market called HBC (High-Bandwidth Compute), to break the memory wall.

Qualcomm's HBC Is A Memory Accelerator That Is Stacked Under DRAM, Offering A Major Boost Versus Standard SRAM & HBM Configurations

At its Investors Day 2026, Qualcomm unveiled HBC, an innovative technology that aims to offer a major boost in memory capacity and bandwidth. The HBC architecture deploys a purpose-built & near-memory solution that bonds compute with boosted memory bandwidth in a 3D stacked chip design. With this, Qualcomm aims to solve the memory bottlenecks that have gripped the tech sector.

Related Story After Earning Major Profits From HBM, SK Hynix Now Plans To Prioritize DDR5 “General-Purpose DRAM” Production

Currently, HBM is the go-to solution for AI Compute accelerators, but it is becoming inefficient due to higher token costs as power continues to climb, which in turn leads to higher TCO.

With HBC (High Bandwidth Compute), Qualcomm claims that the new architecture offers lower energy input per token, increased memory bandwidth, and lowers the TCO. The architecture is built on four fundamentals: 3D integration leadership, System-Level design, LPDDR Leadership, & Power-efficiency expertise.

So how does HBC work? Well, the HBC accelerator sits underneath an LPDDR stack. LPDDR is being selected as the memory choice due to its larger capacities. The LPDDR stack will be interconnected to the HBC accelerator with TSVs (Through-Silicon Vias).

In the first generation or HBC Gen1, the solution will be implemented on the upcoming AI250 accelerator chip, which will have the HBC-boosted LPDDR stack sitting on the same 2D organic substrate. Each AI250 accelerator will feature 133 TB/s of bandwidth per card, an 18x boost over the AI200 with LPDDR5X.

On a competitive level, HBC promises to offer a 6x increase in bandwidth per watt versus HBM, and a 200x increase in capacity per watt versus SRAM. Qualcomm will work with its strategic partners in the supply chain to address the biggest bottleneck that AI faces today, and that is memory capacity, memory bandwidth, and TCO.

The first-generation HBC Gen1 solution with the AI250 AI accelerators is expected to roll out by mid-2027. Qualcomm is also working towards an expanded roadmap and presented the 2nd Generation HBC Gen2 solution for 2028. This solution will be accompanied by the AI300 AI accelerator, and will offer up to 54x speed-up in effective bandwidth versus AI200, and a 7x jump in bandwidth per watt versus HBM.

About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.

Follow Wccftech on Google to get more of our news coverage in your feeds.