Another possible set of GPU die configurations within the AMD RDNA 5 / UDNA lineup has been posted by Kepler_L2, pointing up to 96 CUs.
AMD Might Offer RDNA 5 / UDNA GPU Family In Four Diverse Die Configurations, Top Tier With Up To 96 CUs
Back in July, some early guesswork was done by Kepler_L2 on the upcoming AMD RDNA 5 / UDNA lineup. The leaker has been known for his high accuracy in regards to AMD & Intel-specific info, alongside details of unreleased consoles. He has now posted new information, well, essentially block diagrams of at least four RDNA 5 / UDNA SKUs at Anandtech Forums.
So starting with the top AMD RDNA 5 / UDNA die, it consists of 8 Shader Arrays with two shader engines each for a total of 16 shader engines. Each Shader Engine contains 6 compute units. So 16 shader engines equal a total of 96 Compute Units.
Each Shader Engine has its own RB (Render Backed) unit, & these are connected to a SoC block in the middle, which contains the Graphics Command Processor, Graphics Engine, HWS, and L2 cache. There are also 16 Unified Memory controllers, each 32-bit, for a max bus size of 512-bit. The top die could pack up to 128 MB of Infinity Cache if AMD sticks with the current IFC config.
Moving down the stack, we have the 40 CU die, which could contain five CUs per Shader Engine, and there are 8 Shader Engines in total, arranged in 4 Shader Arrays, providing a total of 40 Compute Units. There are 6 memory controllers, so this gives us a 192-bit bus interface. This variant could get up to 48 MB of total Infinity Cache. Once again, the modularity of its RDNA 5 SoCs, which were hinted at during Hot Chips, will lead to several configurations based around the top die.
The entry-level AMD RDNA 5 / UDNA dies scale from 24 to 12 CUs. The 24 CU die contains four shader engines/arrays with 6 compute units per shader engine for a total of 24 compute units and features a total of 8 memory controllers. These could either be 16-bit (128-bit max) or 32-bit (256-bit) controllers. It may seem unlikely that AMD would go 256-bit on this configuration and not the 40 CU SKU.
The most entry-level die features just two shader arrays/engines with 6 compute units for a total of 12 CUs. This is equipped with four memory controllers, so either 128-bit (32-bit) or 64-bit (16-bit). These smaller dies might pack 32 and 16 MB of Infinity Cache, respectively.
Kepler also opens up the possibility of seeing bigger local cache sizes per CU. He states that the Instinct lineup went from 32KB L0 and 160 KB LDS cache on CDNA 4 to 448 KB of Shared L0/LDS cache on the next-gen CDNA 5 architecture, which will be introduced in the MI400 series. Now, these are datacenter parts, so we can't say for sure that these changes will be brought down to consumer-tier chips, but the next lineup is said to unify Radeon and Instinct architectures, hence the UDNA designation.
Also, one RDNA 5 Compute Unit is essentially a single RDNA 4 WGP. The WGPs or Work Group Processor on RDNA 4 packed two Compute Units so it looks like we are looking at twice the number of cores, or 2x the CU count than what's reported here. Whatever AMD plans to choose will be decided by them and will be final but we have to wait for official details till then.
Also, it looks like that the RDNA 4 lineup may indeed feature four configurations according to Chiphell forum member ZhangZhonghao, who has been very accurate with his past leaks. He alleges that the top-most die would be very large, followed by a mid-tier, a small-tier and a tiny-tier SKU.
Once again, like the previous rumor, this should also be taken with a grain of salt. AMD's next-gen gaming lineup is expected to enter mass production by Q2 2026, so it will be some time before we get any concrete information. This will be around the same time NVIDIA will have its "SUPER" series out, while Intel will probably release its BMG-G31 "Big Battlemage" lineup. So, as far as GPUs are concerned, the start of 2026 should be very exciting for PC gamers.
Potential AMD RDNA 5 / UDNA GPU Configurations (via Kepler_L2):
| GPU Die | Navi 5X | Navi 5X | Navi 5X | Navi 5X |
|---|---|---|---|---|
| Positioning | Flagship-Tier | Mid-Tier | Low-Tier | Entry-Tier |
| Max Compute Units | 96 CUs (12288 Cores) | 40 CUs (5120 Cores) | 24 CUs (3072 Cores) | 12 CUs (1536 Cores) |
| Max Memory Bus | 512-384 bit | 384-192 bit | 256-128 bit | 128-64 bit |
| Max VRAM Capacity | 24-32 GB | 12-24 GB | 8-16 GB | 8-16 GB |
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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