PCIe 6.0 Specification Progress Now At Final Draft, Data Transfer Speeds As High As 128 GB/s

PCIe 6.0 Specification Progress Now At Final Draft, Data Transfer Speeds As High As 128 GB/s

PCI-SIG revealed earlier this week that PCIe 6.0 specification has reached the Final Draft stages—an important and much-needed step that shows completion of the Gen 6 PCIe technology. Any current SoCs conformable with version 0.9 specs will now be accessible to the new 1.0 versions. The only uncertainty is what applications need to upgrade and prepare for the PCIe 6.0 technology.

PCIe 6.0 Standard Almost Finalized, Hits Bandwidth of Up To 128 GB/s

PCIe 6.0 is listed to increase data transfer rates to 64 GT/s per pin, which is an increase from PCIe 5.0 speeds of 32 GT/s. The new technology will remain backward compatible with any current existing hardware. PCIe will now be capable of data transfers of 128 Gb/s in all directions on the x16 interfacing.

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There are five main checkpoints that PCI Express specs have to comply with—Concept, First Draft, Complete Draft, Final Draft, and lastly, Final. Version 0.7 of PCIe Gen 6 was the Complete Draft, which appeared less than a year ago, allowing large corporations and major tech developers, such as Synopsys, to begin utilizing the "PCIe 6.0 controller IP and PHY in silicon." The Final Draft version of PCIe 6.0 (version 0.9), allowed for members of the PCI-SIG to review the new standards for not only patents but also intellectual properties. From that point forward, no changes were permissible by PCI Express.

Manufacturers and developers utilizing PCIe Gen 6 version 1.0 had to create specific standards so that they could reach such high data transfer rates. Companies were expected to "adopt pulse amplitude modulation with four levels (PAM-4) or signaling, which is also used for high-end networking technologies like InfiniBand as well as GDDR6X memory." PCIe 6.0 showcases forward error correction (FEC) at minimal latencies so that it can allow for not only high rates of data but also remain extremely efficient.

The only hurdles for developers now are both cost and concerns overpower. PAM-4 is an expensive endeavor when it comes to both size of the die and in power, which will cause manufacturers to reduce costs were accessible to conform to the newest PCIe 6.0 technology. It is unclear how soon consumers will see developments utilizing the PCIe Gen 6 system, especially causing developers to find an affordable solution.

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