NVIDIA's next-gen Rosa CPUs are expected to utilize TSMC's latest process technologies, such as 2nm & A16 with Super Power Rail.
NVIDIA Eyes TSMC 2nm & A16 Process Technologies For Its Next-Gen Rosa CPUs, Super Power Rail Could Be A Game-Changer
NVIDIA has reportedly tapped TSMC to make its next-gen Rosa CPUs, which arrive in 2029. The CPU was detailed just a day ago, and now, reports are emerging as to what process technologies will be employed by the chip.
It is reported by Commercial Times that NVIDIA is considering the use of two key TSMC process technologies, either 2nm or A16. TSMC's N2P is already being used to produce several chips like AMD's EPYC Venice, Intel's Nova Lake, and more. Samsung is also racing to build & streamline its 2nm technologies to compete with TSMC and Intel.
But for Rosa CPUs, NVIDIA is showing more interest in the A16 process technology, especially due to its Super Rail Power feature, which includes backside power delivery. With this technology, the nanosheet transistors will dedicate the front-side to signal and clock distribution while the back-side will be dedicated to power distribution.
Semiconductor industry insiders speculate that Rosa is likely to be manufactured using TSMC's 2nm family of processes, and may even incorporate A16 back-end power supply technology, driving up demand for CMP (chemical mechanical polishing) processes and consumables.
via Commercial Times
Super Rail Power on A16 improves logic density and performance, with an 8-10% speedup over N2P, and a 15-20% power saving at the same speed. It also offers a 10% increase in chip density. Most importantly, all of these features are incorporated within the same layout footprint.
The use of A16 will also drive up demand for CMP (Chemical Mechanical Polishing) processes, benefiting Taiwanese supply chain partners such as Suntech Power Semiconductor and Suntech Power Technology. Demand for carrier wafers is also expected to witness an uptick.
Rosa Is The Continuation of Leading-Edge AI CPUs
NVIDIA has said that its Rosa CPUs will utilize a brand new core architecture called "Rigel," which is based on the Arm v9.2 CPU core. Like Vera, Rosa will be a really fast chip for AI processing, achieving even more "max single-threaded" CPU performance at scale than its predecessor.
While Vera utilizes the Olympus cores, which are custom Armv9.2-A cores that offer 2x the throughput versus Grace, Rosa will take the single-core performance advantage even further. What's more impressive is that the performance uplift will be achieved in the same silicon footprint.
| Feature | Grace CPU | Vera CPU | Rosa CPU |
|---|---|---|---|
| Status / Availability | Shipping (since 2023) | In production (2026, powers Vera Rubin systems) | Expected 2028 (with Feynman GPUs) |
| Core Architecture | Arm Neoverse V2 (Armv9, licensed) | Custom NVIDIA Olympus (Armv9.2, in-house) | Custom NVIDIA Rigel (Armv9.2, in-house) |
| Cores per CPU | 72 | 88 | TBD |
| Threads per CPU | 72 | 176 (via Spatial Multithreading) | TBD |
| IPC / Per-Core Perf | Baseline (Neoverse V2) | ~50% higher IPC than Grace (Olympus) | Higher per-core than Olympus; focus on ultimate single-thread performance |
| L2 Cache per Core | 1 MB | 2 MB (double Grace) | Larger than Olympus (explicit improvement) |
| Memory Type | LPDDR5X with ECC | LPDDR5X with ECC + SOCAMM / LPDDR6 (RTX Spark) | LPDDR6 / LPDDR6X (RTX Spark)? |
| Memory Bandwidth | Up to ~480–512 GB/s per CPU | Up to 1.2 TB/s (2–3× higher per core vs leading x86) | TBD (expected further gains in efficiency) |
| Memory Capacity | Up to ~480–512 GB per CPU | Up to 1.5 TB | TBD |
| Die Design | Monolithic per CPU (Superchip pairs two via NVLink-C2C) | Monolithic compute die (avoids chiplet latency) | TBD (likely monolithic evolution) |
| Key Interconnect | 1st-gen SCF; NVLink-C2C 900 GB/s (Superchip) | 2nd-gen SCF (3.4 TB/s bisection); NVLink-C2C up to 1.8 TB/s | TBD (further improvements expected) |
| Power Efficiency Focus | 2× performance at the same power vs leading x86 (at launch) | High sustained per-core perf + low memory power (<40W for memory subsystem in some configs) | Ultimate single-thread efficiency |
| Primary Design Goal | Balanced high-core-count efficiency for accelerated/HPC workloads | Max single-threaded performance at scale for agentic AI loops | Ultimate single-thread performance (evolution of Vera's philosophy) |
Rosa should enter the market by 2029 in data centers, followed by PC-specific variants in the Rosa Feynman Spark solutions by 2030.
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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