JEDEC continues the development of DDR5 MRDIMM memory for next-gen datacenters, now offering increased bandwidth.
MRDIMM DDR5 Memory is designed to meet the growing bandwidth & Capacity Demands of AI Datacenters & JEDEC just unleashed its fastest design yet
Two years ago, the first DDR5 MRDIMM memory was announced, offering up to 256 GB capacities per module and 8800 MT/s speeds. Now, as AI & datacenter requirements continue to grow, JEDEC is advancing its MRDIMM roadmap ahead with faster modules that operate at speeds of up to 12,800 MT/s, marking a 45% uplift over the initial design.
Press Release: JEDEC today announced milestones from its JC-40 and JC-45 Committees for Logic and DRAM Modules: the publication of a new DDR5 multiplexed rank data buffer (MDB) standard; progress toward a multiplexed rank registering clock driver (MRCD) standard; and continued work on the DDR5 multiplexed rank DIMM (MRDIMM) Gen2 roadmap to enable higher-bandwidth DDR5 MRDIMM designs.
- Published: JESD82-552 (DDR5MDB02) Multiplexed Rank Data Buffer
- Expected soon: JESD82-542 (DDR5MRCD02) Multiplexed Rank Registering Clock Driver
- In progress: MRDIMM Gen2 module standard nearing completion
- In development: Gen2 DDR5 MRDIMM raw card designs targeting 12,800 MT/s and MRDIMM Gen3 module standard development, with the underlying memory interface logic nearing finalization
Published: JEDEC has published JESD82-552: DDR5MDB02 Multiplexed Rank Data Buffer, now available for download from the JEDEC website. The standard defines next-generation data buffer functionality for multiplexed rank DIMM architectures, supporting robust operation as module bandwidth scales.
Expected soon: JESD82-542: DDR5 Multiplexed Rank Registering Clock Driver (DDR5MRCD02) is expected to be published in the near future. This forthcoming standard is intended to further strengthen signal integrity and timing control in DDR5 MRDIMM module designs, complementing JESD82-552.
In progress: The JC-45 Committee is nearing completion of its MRDIMM Gen2 standard, advancing high-performance memory module design to meet increasing bandwidth and system-level efficiency requirements for next-generation computing platforms.
In development: The committee is also developing second-generation DDR5 MRDIMM Gen2 raw card designs targeting 12,800 MT/s, underscoring JEDEC’s commitment to enabling higher data rates and scalable memory solutions for data-intensive applications. JC-45 is also looking ahead to the development of the MRDIMM Gen3 standard.
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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