The latest Intel patent EP4579444A1 shows how Intel is aiming for improved single-core performance without relying on just hardware scaling.
Intel Files Patent For Software Defined Super Cores; Smaller Cores Work Together as a Bigger Super Core to Enhance Single-Threaded Performance
Intel's latest patent shows that the company wants to improve the single-threaded performance of its CPUs in a way that doesn't require it to scale the hardware. Traditionally, large cores are deployed in a CPU, which have their limits. A single very large core may have diminishing returns, and instead of relying on smaller process nodes and higher frequencies, Intel's new patent EP4579444A1 shows how the company can overcome this challenge through what it calls SDC or Software Defined Super Cores.
SDC is Intel's idea to utilize more cores than a single large core, but fuse them virtually whenever needed. So, for instance, two smaller cores can work together instead of a larger one by dividing the workload, with the goal of enhancing single-threaded performance noticeably. However, this does come with multiple challenges, as splitting the tasks across multiple cores while keeping the program order is quite difficult. However, the new patent claims that SDC is able to maintain the instructions in the correct order, while to the software, it will still appear like a single larger core executing a single thread.
In simple words, a job is assigned to two people instead of one, but they both share the same task to complete it faster. This might seem like multi-threading, but SDC's goal is to target single-threaded operations with this approach. Not only will this aggregate the IPCs to boost single-threaded performance, but it can reportedly do so without increasing the voltage or frequency. Through dynamic fusion, whenever a heavier single-threaded work needs to be executed, the CPU can create a "super core" to complete the job faster.
SDC essentially involves splitting the instructions. It first splits the load across multiple smaller cores and then the cores coordinate in order to maintain the ordering. Then, through mechanisms like the Shadow Store Buffer, it can ensure proper data transfers between the cores. We will see how this works out for Intel because there are still several challenges Intel has to go through, including synchronization complexity, as low-latency inter-core communication is essential, and the way the OS recognizes and assigns the workloads to SDC-enabled cores.
News Sources: Videocardz, Intel Patent
About the author: Sarfraz Khan is a hardware reporter with a focus on PC components and the builder community. With years of experience writing about PC hardware and laptops, his work has been featured on several reputable technology publications. Sarfraz's hands-on experience is demonstrated through his first-person accounts of using and comparing different hardware configurations, providing practical and relatable insights for everyday users. His technical analysis is respected by peers in the enthusiast community and has been cited by specialized hardware sites such as Germany's Igor's Lab.
Follow Wccftech on Google to get more of our news coverage in your feeds.
