Chinese chip maker Innosilicon has announced that its LPDDR6/5X memory controller IP has been delivered to its first domestic customers.
LPDDR6/5X Memory Controller IP From China Sees Its First Customers Lining Up, Supports Up To 14.4 Gbps Speeds
Last year, Innosilicon announced its LPDDR6/5X PHY and Controller IP, which will be used to power the next-generation memory standards. Today, the company announced that they have achieved the first domestic commercial cooperation.
According to Innosilicon, the new LPDDR6/5X PHY + IP Controller combo is designed around an advanced FinFET process technology, offering low-power operation, high bandwidth, and low latency in a multi-packaged controller with several other core advantages. The company says that its expertise in other DRAM technologies, such as GDDR6, GDDR6X, and GDDR7, along with HBM3E and HBM4, has helped it develop a robust LPDDR6/5X solution for the mass market.
LPDDR6-Specific Features
- I/O speed up to 14.4Gbps
- ECS (auto/manual) and Link ECC support
- System Meta Function Mode
- Dual/Per/All Bank Refresh (single/burst)
- Read-Modify-Write with Mask Write support
- Dynamic write NT-ODT
- DVFSL mode
- x24/x48 burst modes
- Normal and dynamic/static efficiency modes
LPDDR6/5X Common Features
- Flexible data width expansion: x12 to x48 (LPDDR6), x16 to x32 (LPDDR5X)
- Built-in performance monitor
- Tx pre-emphasis and Rx DFE to improve signal integrity
- LPDDR5X WCK mode and Link ECC support
- PoP and discrete memory package support
- Single Rank and Multi-Rank configurations
- PVT compensation and timing calibration for all corner reliability
- At-speed BIST, Scan Insertion, PAD and Internal Loopback support
- Multiple low-power modes, including Idle auto-gating, SDRAM self-refresh/power-down, and power-down retention
- Low jitter with superior noise rejection
- Configurable via APB/AHB/AXI register interfaces
To achieve high-speed capabilities of its LPDDR6/5X Combo IP controller, Innosilicon utilized a custom IO architecture design along with process optimizations for SIPI simulation. These enabled a 1.5x increase vs their existing LPDDR5X solution that caps out at 9.6 Gbps. LPDDR6 also moves from a 16-bit architecture to a 24-bit architecture. This means that the IO rate has increased from 9.6 Gbps to 14.4 Gbps. Plus, it also expands the IO bit size from 8-bit to 12-bit, delivering a single-channel 24-bit architecture with 2x the bandwidth bump.
Innosilicon states that its LPDDR6/5X IP is on track for mass production, and the first products utilizing its technology are expected to launch this year from several partners. It has also worked on a new framework that slashes product development cycles by 30%, helping customers bring out new products in the market at a much faster rate.
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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