At the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), Huawei’s He Tingbo showcased the company’s new “LogicFolding Design” technology during the “New Semiconductor Path in Practice” keynote. Hindered due to the lack of access to specialized EUV machinery, Huawei’s only path to remain a competitive entity against its chipset rivals is to innovate on the packaging side, with the advantages of this design including an impressive 53.5 percent increase in transistor design, along with a frequency boost of 12.7 percent. As for the other benefits, those have been detailed below.
With further innovation, Huawei targets 2031 to reach stable clock speeds of 5.00GHz and a density of 400+ MTR/mm²
In 2026, Huawei’s increased density target for its Kirin SoCs would be 238 MTR/mm², enabling the clock speeds to increase by 12.7 percent, meaning that the performance cores would now operate at 3.10GHz. While this is considerably low when you factor in that Qualcomm is rumored to be testing its Snapdragon 8 Elite Gen 6 Pro at 5.00GHz, it’s still an improvement over the current Kirin 930 Pro, which has its performance cores topped out at 2.75GHz.
Huawei’s LogicFolding Design also improves P-core efficiency by 41 percent, greatly reducing the power consumption of upcoming Kirin SoCs. Combine these improved attributes and silicon-carbon battery technology in Huawei’s Pura and Mate series of smartphones, and we’re expected to witness impressive gains in battery runtimes.
The former Chinese giant also says it’ll continue improving its LogicFolding Design annually, with its targeted frequency for 2031 at 5.00GHz and a transistor density of 400+ MTR/mm². The company also states that by moving to this design, not only will it allow for better transistor density scaling, but it’ll result in 30 percent cost reductions.
The cost-savings part caught our eye because Huawei will introduce this packaging while sticking with the older DUV equipment. To achieve chip lithography at 5nm, DUV machinery needs to resort to multi-patterning techniques, which are both expensive and result in substantial wafer defects. Looking at these trade-offs, Huawei will likely bring some cost savings through its new packaging, and while we’re excited for these innovations, only time will tell how true these figures are, so stay tuned.
About the author: Omar Sohail is a reporter and analyst for Wccftech's mobile section, specializing in the technology and business of the mobile industry. His expertise lies in the intricate hardware supply chain, covering developments in semiconductor manufacturing, chip lithography, and camera sensor technology.
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