Korean AI Startup, Furiosa AI, Is Doubling Its Chip Production To 50,000 Units Next Year While Its Upcoming 2nm “Stork” Chip Challenges NVIDIA With The “World’s Best Inference”

Furiosa AI is all set to double its chip production to 50,000 units as it preps its 2nm "Stork" chip to break NVIDIA's inference dominance.

Furiosa AI Claims Its 3rd Gen "Stork" 2nm Chip To Feature The Best Inference Capabilities On The Market, Will Also Double The Production of 2nd Gen Chips Next Year To Break NVIDIA's Monopoly

Back in May, Furiosa AI announced its third-generation AI accelerator chip called Stork for its RNGD (Renegade) platform. The chip is built on Broadcom's 2nm technology, and the startup claims it will challenge NVIDIA with leading efficiency and the lowest cost per token.

According to industry sources on the 13th, Furiosa AI plans to significantly expand the production volume of its second-generation LLM inference-specialized chip, "Renegade (RNGD)," to 40,000 to 50,000 units by next year. This represents more than a twofold increase compared to this year's 20,000 units. This is the first time that the next-year production plans of Furiosa AI, a leading domestic AI semiconductor company, have been confirmed.

via ETNews

The current 2nm Gen chip has already entered mass production and is expected to see 20,000 units ready in 2026. But Furiosa AI has more ambitious plans laid out for its AI accelerators. These plans include doubling the chip production to 40K-50K units next year. The company has stated that the rapid surge in AI inference has led them to double production as they anticipate huge demand based on their recent highlights.

Furiosa AI's Stork Chip - A 2nm AI Inference Disruptor

The next-generation design is going to go all-in on the AI inference segment as Agentic AI continues to see huge demand. The third-generation AI accelerator from FuriosaAI has the following highlights:

• The platform pairs 2nm compute technology with HBM4/4E memory, designed to enable high-bandwidth, rack-scale networking across massive AI compute clusters. 
• The architecture is optimized for demanding inference workloads with a focus on high-bandwidth data movement that delivers higher performance-per-watt and greater token density than even the most efficient GPUs.
• It builds on Furiosa’s current-generation RNGD chip, now in mass production. Customers include Samsung SDS and LG AI Research.

Starting with some of the details shared by FuriosaAI, the Stork AI chip platform will utilize an advanced 2nm compute die and HBM4/E memory standard. The firm is working with Broadcom to harness advanced packaging capabilities, allowing them to integrate multiple silicon dies into a singular & performant AI chip (System-on-chip).

In the teaser shot, the company shows the 3rd Gen AI chip with 12 HBM4/E memory sites, two massive compute chiplets (2nm), and two IO controllers. That rounds up to 432 GB if Furiosa uses 12-Hi 36 GB per stack of memory modules.

Besides the compute architecture, FuriosaAI will also leverage Broadcom's Ethernet and PCIe IPs, allowing higher bandwidth, rack-scale networking across massive AI compute clusters. The AI chip is optimized for demanding real-world AI workloads such as post-training sampling, and high bandwidth is a key focus & that's why the company is going with the latest HBM4/E standards.

The company claims that its focus on bandwidth rather than thread management (required by GPUs) will help it deliver higher efficiency and higher token throughput than modern GPU designs. Furthermore, the company is saying that its software stack allows developers to deploy new AI models quickly while meeting throughput and latency requirements.

Furiosa’s SDK leverages a general compiler that automatically maps high-level PyTorch code to silicon. For developers requiring more granular control, Furiosa’s Virtual ISA offers a declarative programming model that provides hardware control without the nondeterministic complexity of traditional GPU programming.

“Bringing together Broadcom’s infrastructure capabilities and Furiosa’s Tensor Contraction Processor architecture and its industry-defining software stack allows us to move beyond the chip level and deliver a comprehensive solution for the token factory era,” said Furiosa Cofounder and CEO June Paik.

As for availability, the 3rd Gen FuriosaAI accelerator is expected to begin sampling in the first half of 2028 and will be ready to meet compute requirements for next-gen AI data centers.

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