TSMC might be making waves of progress with its 2nm node, as it has been reported to achieve a 60 percent yield on its cutting-edge node during trial production. However, there is no guarantee that its customers will be utilizing this technology any time soon, at least according to one report. Apple, who has consistently tried to gain an advantage over the competition by shifting to newer processes for a variety of chipsets, the company may stick with TSMC’s 3nm N3P for the A20, which is scheduled to arrive in late 2026 and will power the iPhone 18 family.
The technology giant is said to introduce its A19 and A19 Pro for the iPhone 17 series later this year, with both Apple Silicon said to be mass produced on TSMC’s third-generation 3nm node. Regarding lithography, the A19, A19 Pro, and the A20 will not share any differences, but one report states that the new SoC could leverage newer packaging to obtain some advantage. It appears that even trillion-dollar entities are not jumping onto the bleeding-edge manufacturing process immediately due to the hefty wafer costs, so it may take a while to make that transition.
TSMC’s CoWoS packaging could be used for Apple’s A20, allowing for a tighter integration of the internals, but no word if there will be performance or efficiency improvements
Various packaging technologies are being explored by Apple to enhance both the performance and power-efficiency attributes of its chipsets. Given that wafer costs will continue to rise as TSMC pushes the technological boundaries at its foundries, companies such as Apple will have to conduct various experiments on how to maintain a competitive advantage while staying on the same lithography, which, in this case, is the 3nm N3P node.
According to a research note from investment firm GF Securities’ analyst Jeff Pu that was spotted by MacRumors, the A20 will shift to TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) packaging. In a nutshell, this packaging allows for the tighter integration of various parts. As the majority of you know, the A20 compromises not only performance and efficiency cores but also the Neural Engine, GPU cluster, cache, and other components.
By using TSMC’s CoWoS technology, all of these parts can be placed tightly together, saving up valuable space and leading to better efficiency. Additionally, CoWoS can boost performance by reducing signal path lengths and improving data transfer rates. Apart from CoWoS, Apple is also said to be exploring TSMC’s Small Outline Integrated Circuit Molding-Horizontal (SoIC-MH) packaging for the higher-end M5 SoC, suggesting that we could see such techniques being employed in favor of gravitating to newer manufacturing processes.
About the author: Omar Sohail is a reporter and analyst for Wccftech's mobile section, specializing in the technology and business of the mobile industry. His expertise lies in the intricate hardware supply chain, covering developments in semiconductor manufacturing, chip lithography, and camera sensor technology.
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