AMD has confirmed its next-gen product lineups, including Zen 6-based EPYC Venice, Zen 7-based EPYC Verano, and Instinct MI500 series.
AMD EPYC Venice With Zen 6 In 2026 & Next-Gen EPYC Verano With Zen 7 In 2027, Up To 256 Cores Next Year With Instinct MI500 Series For Next-Gen Rack In 2027
Wrapping up its Advancing AI keynote, AMD confirmed its next-generation EPYC and Instinct family lineups.
During its keynote, AMD confirmed that next year, it will introduce its Instinct MI400 series, which offers a 10x performance uplift over the MI350 series that launched today. The company is also announcing some key details of its next-generation EPYC lineup, codenamed "Venice." The lineup will incorporate the brand-new Zen 6 architecture that debuts next year and features up to 256 cores.
Based on previous reports, AMD's 6th Gen EPYC Venice CPUs will come in two flavors, just like the Zen 5 and Zen 4 offerings, a standard Zen 6 variant and a denser Zen 6C variant. These will be featured in the SP7 and SP8 sockets, with the former being the higher-end solution while the latter aims at the entry-level server solutions. The platform will come with both 16 & 12-channel memory support.
In terms of core counts, the AMD EPYC 9006 "Venice" CPUs will have up to 96 cores and 192 threads with up to 8 CCDs in classic configurations, while Zen 6C variants will scale up to 256 cores and 512 threads.
- EPYC 9006 "Venice" With Zen 6C: 256 Cores / 512 Threads / Up To 8 CCDs
- EPYC 9005 "Turin" With Zen 5C: 192 Cores / 384 Threads / Up To 12 CCDs
- EPYC 9006 "Venice" With Zen 5: 96 Cores / 192 Threads / Up To 8 CCDs
- EPYC 9005 "Turin" With Zen 5: 96 Cores / 192 Threads / Up To 16 CCDs
The chips will be fabricated on TSMC's 2nm process node and offer up to 2x the CPU-to-GPU bandwidth with a 70% gen-on-gen performance gain and up to 1.6 TB/s of memory bandwidth. The AMD EPYC Venice CPUs, Instinct MI400 series, and Vulcano FPGAs will be packed within the Helios data center rack in 2026.
In 2027, AMD will be introducing its next-gen EPYC Verano CPUs and Instinct MI500 series. The EPYC Verano CPUs are likely going to utilize either an upgraded version of Zen 6 or next-gen Zen 7 core architecture since AMD is shifting to an annual cadence, so we are going to see updates on the datacenter and AI front at a very rapid pace, similar to what NVIDIA is doing now with a standard and an "Ultra" offering. These will be used to power the next-gen AI racks and will offer a disruptive uplift in overall performance.
AMD EPYC CPU Families:
| Family Name | AMD EPYC Verano | AMD EPYC Venice | AMD EPYC Turin-X | AMD EPYC Turin-Dense | AMD EPYC Turin | AMD EPYC Siena | AMD EPYC Bergamo | AMD EPYC Genoa-X | AMD EPYC Genoa | AMD EPYC Milan-X | AMD EPYC Milan | AMD EPYC Rome | AMD EPYC Naples |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Family Branding | EPYC 9007 | EPYC 9006 | EPYC 9005 | EPYC 9005 | EPYC 9005 | EPYC 8004 | EPYC 9004 | EPYC 9004 | EPYC 9004 | EPYC 7004 | EPYC 7003 | EPYC 7002 | EPYC 7001 |
| Family Launch | 2027 | 2026 | 2025 | 2025 | 2024 | 2023 | 2023 | 2023 | 2022 | 2022 | 2021 | 2019 | 2017 |
| CPU Architecture | Zen 7 | Zen 6 | Zen 5 | Zen 5C | Zen 5 | Zen 4 | Zen 4C | Zen 4 V-Cache | Zen 4 | Zen 3 | Zen 3 | Zen 2 | Zen 1 |
| Process Node | TBD | 2nm TSMC | 4nm TSMC | 3nm TSMC | 4nm TSMC | 5nm TSMC | 4nm TSMC | 5nm TSMC | 5nm TSMC | 7nm TSMC | 7nm TSMC | 7nm TSMC | 14nm GloFo |
| Platform Name | SP7 | SP7 | SP5 | SP5 | SP5 | SP6 | SP5 | SP5 | SP5 | SP3 | SP3 | SP3 | SP3 |
| Socket | TBD | TBD | LGA 6096 (SP5) | LGA 6096 (SP5) | LGA 6096 | LGA 4844 | LGA 6096 | LGA 6096 | LGA 6096 | LGA 4094 | LGA 4094 | LGA 4094 | LGA 4094 |
| Max Core Count | TBD | 96 | 128 | 192 | 128 | 64 | 128 | 96 | 96 | 64 | 64 | 64 | 32 |
| Max Thread Count | TBD | 192 | 256 | 384 | 256 | 128 | 256 | 192 | 192 | 128 | 128 | 128 | 64 |
| Max L3 Cache | TBD | TBD | 1536 MB | 384 MB | 384 MB | 256 MB | 256 MB | 1152 MB | 384 MB | 768 MB | 256 MB | 256 MB | 64 MB |
| Chiplet Design | TBD | 8 CCD's (1 CCX per CCD) + 2 IOD? | 16 CCD's (1CCX per CCD) + 1 IOD | 12 CCD's (1CCX per CCD) + 1 IOD | 16 CCD's (1CCX per CCD) + 1 IOD | 8 CCD's (1CCX per CCD) + 1 IOD | 12 CCD's (1 CCX per CCD) + 1 IOD | 12 CCD's (1 CCX per CCD) + 1 IOD | 12 CCD's (1 CCX per CCD) + 1 IOD | 8 CCD's (1 CCX per CCD) + 1 IOD | 8 CCD's (1 CCX per CCD) + 1 IOD | 8 CCD's (2 CCX's per CCD) + 1 IOD | 4 CCD's (2 CCX's per CCD) |
| Memory Support | TBD | DDR5-12800 | DDR5-6000? | DDR5-6400 | DDR5-6400 | DDR5-5200 | DDR5-5600 | DDR5-4800 | DDR5-4800 | DDR4-3200 | DDR4-3200 | DDR4-3200 | DDR4-2666 |
| Memory Channels | TBD | 16-Channel (SP7) | 12 Channel (SP5) | 12 Channel | 12 Channel | 6-Channel | 12 Channel | 12 Channel | 12 Channel | 8 Channel | 8 Channel | 8 Channel | 8 Channel |
| PCIe Gen Support | TBD | 128-192 PCIe Gen 6 | TBD | 128 PCIe Gen 5 | 128 PCIe Gen 5 | 96 Gen 5 | 128 Gen 5 | 128 Gen 5 | 128 Gen 5 | 128 Gen 4 | 128 Gen 4 | 128 Gen 4 | 64 Gen 3 |
| TDP (Max) | TBD | ~600W | 500W (cTDP 600W) | 500W (cTDP 450-500W) | 400W (cDP 320-400W) | 70-225W | 320W (cTDP 400W) | 400W | 400W | 280W | 280W | 280W | 200W |
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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