AMD has revealed that the company is considering chiplet designs for its Ryzen APU family for laptops but cost & power are the main barriers.
AMD Would Consider A Chiplet Design For Ryzen APUs In Laptop Segment Once Power & Cost Barriers Are Overcome
Switching to a chiplet-based configuration is the next big thing in the industry, and for those who are unaware of what a chiplet actually is, it is a combination of different chips integrated into a single package, with an interconnected system that significantly contributes towards the idea of "process shrinking". You can have multiple chiplets of the same core IP or different ones and the designs can be mixed-matched to deliver the best suitable performance for a product segment.
Chiplet designs are rivaled by the traditional monolithic configuration, which has been present for several years in the industry and is the complete opposite of how chip designs are configured. But while monolithic designs are shrinking, especially in the high-end segment, it looks like AMD still believes the monolithic chips serve a good purpose in the mainstream laptop segment with its Ryzen APU series.
AMD has revealed that the company would consider taking the "chiplet" route in mainstream Ryzen APUs, however, it is hesitant for now due to the constraints that the design comes with. While chiplet configuration comes with several advantages such as the ability to shrink individual nodes, target specialized workloads, and reduce costs, the one thing it lacks is maintaining power efficiency. The factor was highlighted by David Afee Corporate VP and General Manager, Client Channel Business at AMD in a Q&A session in South Korea, where he believes that now isn't the best time to switch to chiplet designs for power-efficient chips.
Q. Although AMD has achieved success in the desktop market through its chiplet architecture, it maintains a single chip, monolithic structure in the laptop market. I wonder why this chiplet architecture hasn't been introduced yet in the laptop market, especially the ultra-mobile market.
A.When creating the product, we are considering both monolithic and chiplet structures. Both desktops and laptops. However, on the laptop side, it is difficult to introduce chiplets because of the major obstacle of power. Since there is a power penalty to be paid when introducing chiplets, it seems that chiplets can be introduced at a time when it is judged to be worth it.
So far, considering such factors, the results have shown that monolithic structures are more cost-effective and efficient than chiplets in the laptop market. If there is an incentive to risk it and move in the future, I think I would consider a chiplet.
David McAfee (AMD Corporate VP and General Manager, Client Channel Business at AMD) via Quasarzone
So not only is power a main concern but also the cost-effectiveness of using the chiplet designs. It looks like as entry-level or mainstream you go, chiplets don't yield the same cost-effectiveness as a monolithic die. That's one way to think about it but on the other hand, we have seen AMD adopting chiplets for its high-end Dragon Range CPUs for enthusiast-grade laptops. Considering that these are enthusiast products in high-end designs, the power and cost issues aren't a huge deal here.
It's also expected that AMD will be using a chiplet-based design for its next-gen Strix Point (Halo) chips launching next year but the details on that family are still slim right now. The lineup will also come in the standard monolithic layout so the full realization of chiplets in the mainstream laptop "Ryzen APU" segment shouldn't be expected until 2026-2027. Intel is also following the chiplet path with its Meteor Lake and future CPUs which utilize a fully disaggregated chip design with multiple tiles hosting multiple core IPs and IO capabilities.
For now, the implementation of power-efficient "chiplet-based" for Ryzen APUs is yet to be seen, however, it looks like AMD is indeed planning for it. The company was definitely the first to see the potential of chiplets and was the first to bring them to mainstream and high-end users on both desktop and laptop platforms. We can't wait to see what AMD will have in store with its first Ryzen APUs featuring a monolithic design.
AMD Ryzen Mobility CPUs:
| CPU Family Name | AMD Sound Wave? | AMD Bald Eagle Point | AMD Krackan Point | AMD Fire Range | AMD Strix Point Halo | AMD Strix Point | AMD Hawk Point | AMD Dragon Range | AMD Phoenix | AMD Rembrandt | AMD Cezanne | AMD Renoir | AMD Picasso | AMD Raven Ridge |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Family Branding | TBD | Ryzen AI 400 | TBD | TBD | Ryzen AI 300 | Ryzen AI 300 | AMD Ryzen 8040 (H/U-Series) | AMD Ryzen 7045 (HX-Series) | AMD Ryzen 7040 (H/U-Series) | AMD Ryzen 6000 AMD Ryzen 7035 | AMD Ryzen 5000 (H/U-Series) | AMD Ryzen 4000 (H/U-Series) | AMD Ryzen 3000 (H/U-Series) | AMD Ryzen 2000 (H/U-Series) |
| Process Node | TBD | 4nm | 4nm | 5nm | 4nm | 4nm | 4nm | 5nm | 4nm | 6nm | 7nm | 7nm | 12nm | 14nm |
| CPU Core Architecture | Zen 6? | Zen 5 + Zen 5C | Zen 5 | Zen 5 | Zen 5 + Zen 5C | Zen 5 + Zen 5C | Zen 4 + Zen 4C | Zen 4 | Zen 4 | Zen 3+ | Zen 3 | Zen 2 | Zen + | Zen 1 |
| CPU Cores/Threads (Max) | TBD | 12/24 | 8/16 | 16/32 | 16/32 | 12/24 | 8/16 | 16/32 | 8/16 | 8/16 | 8/16 | 8/16 | 4/8 | 4/8 |
| L2 Cache (Max) | TBD | 12 MB | TBD | TBD | 24 MB | 12 MB | 4 MB | 16 MB | 4 MB | 4 MB | 4 MB | 4 MB | 2 MB | 2 MB |
| L3 Cache (Max) | TBD | 24 MB + 16 MB SLC | 32 MB | TBD | 64 MB + 32 MB SLC | 24 MB | 16 MB | 32 MB | 16 MB | 16 MB | 16 MB | 8 MB | 4 MB | 4 MB |
| Max CPU Clocks | TBD | TBD | TBD | TBD | TBD | 5.1 GHz | TBD | 5.4 GHz | 5.2 GHz | 5.0 GHz (Ryzen 9 6980HX) | 4.80 GHz (Ryzen 9 5980HX) | 4.3 GHz (Ryzen 9 4900HS) | 4.0 GHz (Ryzen 7 3750H) | 3.8 GHz (Ryzen 7 2800H) |
| GPU Core Architecture | RDNA 3+ iGPU | RDNA 3.5 4nm iGPU | RDNA 3+ 4nm iGPU | RDNA 3+ 4nm iGPU | RDNA 3.5 4nm iGPU | RDNA 3.5 4nm iGPU | RDNA 3 4nm iGPU | RDNA 2 6nm iGPU | RDNA 3 4nm iGPU | RDNA 2 6nm iGPU | Vega Enhanced 7nm | Vega Enhanced 7nm | Vega 14nm | Vega 14nm |
| Max GPU Cores | TBD | 16 CUs (1024 Cores) | 12 CUs (786 cores) | 2 CUs (128 cores) | 40 CUs (2560 Cores) | 16 CUs (1024 Cores) | 12 CUs (786 cores) | 2 CUs (128 cores) | 12 CUs (786 cores) | 12 CUs (786 cores) | 8 CUs (512 cores) | 8 CUs (512 cores) | 10 CUs (640 Cores) | 11 CUs (704 cores) |
| Max GPU Clocks | TBD | 2900 MHz | TBD | TBD | TBD | 2900 MHz | 2800 MHz | 2200 MHz | 2800 MHz | 2400 MHz | 2100 MHz | 1750 MHz | 1400 MHz | 1300 MHz |
| TDP (cTDP Down/Up) | TBD | 15W-45W (65W cTDP) | 15W-45W (65W cTDP) | 55W-75W (65W cTDP) | 55W-125W | 15W-45W (65W cTDP) | 15W-45W (65W cTDP) | 55W-75W (65W cTDP) | 15W-45W (65W cTDP) | 15W-55W (65W cTDP) | 15W -54W(54W cTDP) | 15W-45W (65W cTDP) | 12-35W (35W cTDP) | 35W-45W (65W cTDP) |
| Launch | 2026? | 2025? | 2025? | 2H 2024? | 2H 2024? | 2H 2024 | Q1 2024 | Q1 2023 | Q2 2023 | Q1 2022 | Q1 2021 | Q2 2020 | Q1 2019 | Q4 2018 |
News Source: QuasarZone
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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