AMD has confirmed that its next-gen MI500 AI accelerator will utilize the CDNA 6 architecture & an advanced 2nm node.
AMD MI500 AI Accelerator Launches In 2027: Powered By Advanced 2nm Process, CDNA 6 Architecture & HBM4E Memory
In 2027, AMD will be introducing its next-gen Instinct MI500 series AI accelerators. Since AMD is shifting to an annual cadence, we are going to see updates on the datacenter and AI front at a very rapid pace, similar to what NVIDIA is doing now with a standard and an "Ultra" offering. These will be used to power the next-gen AI racks and will offer a disruptive uplift in overall performance.
Today, AMD confirmed some additional details of its Instinct MI500 AI accelerators. For starters, the MI500 series will be fabricated on an advanced 2nm process technology. The upcoming MI400 series makes use of a 2nm process technology too, but the one utilized by MI500 is more advanced, & offers various enhancements. The chips will be produced at TSMC.
The next detail is that the MI500 accelerator will leverage the new CDNA 6 architecture (CDNA 5 for MI400 series), and HBM4E memory, which will offer even higher speeds and memory bandwidth than 19.6TB/s on HBM4-powered MI400 accelerators. Also, unlike previous reports, it looks like AMD isn't going to change to the UDNA architecture naming for Instinct GPUs.
Lastly, AMD has promised a big jump in AI performance with the Instinct MI500 series. The company is on the trajectory to achieve over 1000x AI performance in just four years. This is crucial to meet the growing AI demand and keep up with the competition, which is also accelerating at a rapid pace. MI500 launches in 2027.
AMD Instinct AI Accelerators:
| Accelerator Name | AMD Instinct MI500 | AMD Instinct MI400 | AMD Instinct MI350X | AMD Instinct MI325X | AMD Instinct MI300X | AMD Instinct MI250X |
|---|---|---|---|---|---|---|
| GPU Architecture | CDNA 6 | CDNA 5 | CDNA 4 | Aqua Vanjaram (CDNA 3) | Aqua Vanjaram (CDNA 3) | Aldebaran (CDNA 2) |
| GPU Process Node | 2nm | 2nm+3nm | 3nm | 5nm+6nm | 5nm+6nm | 6nm |
| XCDs (Chiplets) | TBD | 8 (MCM) | 8 (MCM) | 8 (MCM) | 8 (MCM) | 2 (MCM) 1 (Per Die) |
| GPU Cores | TBD | TBD | 16,384 | 19,456 | 19,456 | 14,080 |
| GPU Clock Speed (Max) | TBD | TBD | 2400 MHz | 2100 MHz | 2100 MHz | 1700 MHz |
| INT8 Compute | TBD | TBD | 5200 TOPS | 2614 TOPS | 2614 TOPS | 383 TOPs |
| FP6/FP4 Matrix | TBD | 40 PFLOPs | 20 PFLOPs | N/A | N/A | N/A |
| FP8 Matrix | TBD | 20 PFLOPs | 5 PFLOPs | 2.6 PFLOPs | 2.6 PFLOPs | N/A |
| FP16 Matrix | TBD | 10 PFLOPs | 2.5 PFLOPs | 1.3 PFLOPs | 1.3 PFLOPs | 383 TFLOPs |
| FP32 Vector | TBD | TBD | 157.3 TFLOPs | 163.4 TFLOPs | 163.4 TFLOPs | 95.7 TFLOPs |
| FP64 Vector | TBD | TBD | 78.6 TFLOPs | 81.7 TFLOPs | 81.7 TFLOPs | 47.9 TFLOPs |
| VRAM | HBM4E | 432 GB HBM4 | 288 GB HBM3e | 256 GB HBM3e | 192 GB HBM3 | 128 GB HBM2e |
| Infinity Cache | TBD | TBD | 256 MB | 256 MB | 256 MB | N/A |
| Memory Clock | TBD | 19.6 TB/s | 8.0 Gbps | 5.9 Gbps | 5.2 Gbps | 3.2 Gbps |
| Memory Bus | TBD | TBD | 8192-bit | 8192-bit | 8192-bit | 8192-bit |
| Memory Bandwidth | TBD | TBD | 8 TB/s | 6.0 TB/s | 5.3 TB/s | 3.2 TB/s |
| Form Factor | TBD | TBD | OAM | OAM | OAM | OAM |
| Cooling | TBD | Passive / Liquid | Passive / Liquid | Passive Cooling | Passive Cooling | Passive Cooling |
| TDP (Max) | TBD | TBD | 1400W (355X) | 1000W | 750W | 560W |
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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