AMD EPYC Venice “Zen 6C” CPU Die Size Analyzed: 32-Core “Zen 6C” CCDs Almost Twice As Big As Zen 5C CCDs, Dual 375mm²+ IO Dies

AMD's next-generation Zen 6C-based EPYC Venice CPU die has been analyzed, revealing a big bump in both core counts & die size.

AMD Goes Big With Its Next-Gen EPYC Venice "Zen 6C" CPU: Twice As Many Cores Per CCD On 2nm, Two Massive IO Dies

At CES 2026, AMD unveiled its next-generation EPYC Venice CPU based on the brand-new Zen 6 core architecture. The chip features a massive upgrade in terms of core counts, performance, efficiency, & is the world's first data center CPU to feature TSMC's 2nm process technology.

With the EPYC Venice "Zen 6" CPU, AMD is now packing 8 massive Zen 6C CCDs and two IODs, along with smaller chiplets with management controllers. The company has promised over 70% performance & efficiency improvement with its EPYC Venice CPUs, with a >30% increase in thread density. The chip will also come in standard 192-core "Zen 6" flavors, packing 16 CCDs, each with 12 Zen 6 cores, and 768 MB of L3 cache.

Although not as chonky as the MI455X, which is an absolute monster chip, the EPYC Venice is still a huge CPU, featuring up to 256 cores. At the heart of each AMD EPYC Venice CPU is the Zen 6C CCD. These are compute chiplets, comprising 32 "Zen 6C" cores. That's a doubling of the core count versus the Zen 5C CCD with 16 cores per chiplet. Each Zen 6C CCD also packs 128 MB of L3 cache for a total of 1024 MB on the entire chip. The standard Zen 6 CCD will feature 12 cores and 48 MB L3 cache per chiplet.

In terms of die size, each Zen 6C CCD on the AMD EPYC Venice CPUs will measure around 155mm2, which is almost twice as big as the Zen 5C CCDs, which measure around 85mm2. The Zen 6C CCDs are fabricated on the TSMC N2P process technology, while Zen 5C CCDs were fabricated on the TSMC N3E process tech. To be precise, this is a 82.3% die size increase generation over generation, but with a much larger cache, & double the cores.

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Venice IOD: ~375mm² N6 x 2
Turin IOD: ~426mm² N6 x 1

Zen6c CCD: 32 Cores = ~155mm² N2
Zen5c CCD: 16 Cores = ~85mm² N3E https://t.co/n4GJGNWqlo

— Hassan Mujtaba (@hms1193) January 12, 2026

The AMD EPYC Venice CPUs will also pack two massive IO dies, which will feature memory controllers, PCIe controllers, and other IPs, including AI-specific accelerators. Each Venie IOD is based on TSMC's N6 process technology and measures around 375mm2. The previous-gen EPYC Turin CPUs featured a single IO die measuring 426mm2 on the same N6 process tech.

AMD EPYC Venice vs Turin CCD Comparison:

• Zen6c CCD: 32 Cores = ~155mm² N2
• Zen5c CCD: 16 Cores = ~85mm² N3E

AMD EPYC Venice vs Turin IOD Comparison:

• Venice IOD: ~375mm² N6 x 2
• Turin IOD: ~426mm² N6 x 1

AMD EPYC Venice vs Turin CPU Comparison:

• EPYC 9006 "Venice" With Zen 6C: 256 Cores / 512 Threads / Up To 8 CCDs / 1024 MB L3
• EPYC 9005 "Turin" With Zen 5C: 192 Cores / 384 Threads / Up To 12 CCDs / 384 MB L3
• EPYC 9006 "Venice" With Zen 5: 96 Cores / 192 Threads / Up To 8 CCDs / 384 MB L3
• EPYC 9005 "Turin" With Zen 5: 96 Cores / 192 Threads / Up To 16 CCDs / 384 MB L3

With each IO die measuring 375mm2, you are looking at 750mm2 of die space dedicated to just IO. The addition of two dies shows that AMD is going to upgrade the IO capabilities of its next-gen EPYC data-center platforms in a big way. Overall, the AMD EPYC Venice CPUs are going to offer massive amounts of compute capabilities and will be competing against Intel's Diamond Rapids CPUs based on the 18A node. These chips are also expected to come in 256 and 192-core flavors.

AMD EPYC CPU Families:

Family Name	AMD EPYC Verano	AMD EPYC Venice	AMD EPYC Turin-X	AMD EPYC Turin-Dense	AMD EPYC Turin	AMD EPYC Siena	AMD EPYC Bergamo	AMD EPYC Genoa-X	AMD EPYC Genoa	AMD EPYC Milan-X	AMD EPYC Milan	AMD EPYC Rome	AMD EPYC Naples
Family Branding	EPYC 9007	EPYC 9006	EPYC 9005	EPYC 9005	EPYC 9005	EPYC 8004	EPYC 9004	EPYC 9004	EPYC 9004	EPYC 7004	EPYC 7003	EPYC 7002	EPYC 7001
Family Launch	2027	2026	2025	2025	2024	2023	2023	2023	2022	2022	2021	2019	2017
CPU Architecture	Zen 7	Zen 6	Zen 5	Zen 5C	Zen 5	Zen 4	Zen 4C	Zen 4 V-Cache	Zen 4	Zen 3	Zen 3	Zen 2	Zen 1
Process Node	TBD	2nm TSMC	4nm TSMC	3nm TSMC	4nm TSMC	5nm TSMC	4nm TSMC	5nm TSMC	5nm TSMC	7nm TSMC	7nm TSMC	7nm TSMC	14nm GloFo
Platform Name	SP7	SP7	SP5	SP5	SP5	SP6	SP5	SP5	SP5	SP3	SP3	SP3	SP3
Socket	TBD	TBD	LGA 6096 (SP5)	LGA 6096 (SP5)	LGA 6096	LGA 4844	LGA 6096	LGA 6096	LGA 6096	LGA 4094	LGA 4094	LGA 4094	LGA 4094
Max Core Count	TBD	96	128	192	128	64	128	96	96	64	64	64	32
Max Thread Count	TBD	192	256	384	256	128	256	192	192	128	128	128	64
Max L3 Cache	TBD	TBD	1536 MB	384 MB	384 MB	256 MB	256 MB	1152 MB	384 MB	768 MB	256 MB	256 MB	64 MB
Chiplet Design	TBD	8 CCD's (1 CCX per CCD) + 2 IOD?	16 CCD's (1CCX per CCD) + 1 IOD	12 CCD's (1CCX per CCD) + 1 IOD	16 CCD's (1CCX per CCD) + 1 IOD	8 CCD's (1CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (2 CCX's per CCD) + 1 IOD	4 CCD's (2 CCX's per CCD)
Memory Support	TBD	DDR5-12800	DDR5-6000?	DDR5-6400	DDR5-6400	DDR5-5200	DDR5-5600	DDR5-4800	DDR5-4800	DDR4-3200	DDR4-3200	DDR4-3200	DDR4-2666
Memory Channels	TBD	16-Channel (SP7)	12 Channel (SP5)	12 Channel	12 Channel	6-Channel	12 Channel	12 Channel	12 Channel	8 Channel	8 Channel	8 Channel	8 Channel
PCIe Gen Support	TBD	128-192 PCIe Gen 6	TBD	128 PCIe Gen 5	128 PCIe Gen 5	96 Gen 5	128 Gen 5	128 Gen 5	128 Gen 5	128 Gen 4	128 Gen 4	128 Gen 4	64 Gen 3
TDP (Max)	TBD	~600W	500W (cTDP 600W)	500W (cTDP 450-500W)	400W (cDP 320-400W)	70-225W	320W (cTDP 400W)	400W	400W	280W	280W	280W	200W

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