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AMD Zen 6 Architecture Rumored To Power EPYC Venice Server CPUs: Over 200 Cores, Completely Redesigned L2/L3 Cache & HBM SKUs

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The successor to AMD's EPYC Turin CPUs which will feature Zen 5 cores is rumored to be called EPYC Venice and will feature Zen 6 architecture, reports Moore's Law is Dead.

AMD EPYC Venice Server CPUs Rumored To Feature Over 200 Zen 6 Cores With Redesigned L2/L3 Cache & HBM SKUs

While the details are quite vague at the moment considering this product isn't expected to launch till 2025+, it looks like MLID got his hands on very early details regarding the codename and AMD's marketing has come up with 'Venice' for its next-generation EPYC lineup. Named after the capital of the Veneto region in northeastern Italy, the EPYC Venice lineup is expected to be a huge update for servers.

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Some details that are shared include references to the AMD Zen 6 cores though it is not known if the red team will continue with its Zen naming scheme beyond 2025 or move to something else. The server segment will continue with the EPYC naming convention. It is said that Zen 6 or the x86 architecture after Zen 5 will make use of a very hybrid core design approach and can offer over 200 cores (a conservative estimate) with rumors of up to 384 cores per socket. There's no mention if the CPU will be compatible with the SP5 platform but it looks like Turin and its follow-up on Zen 5C might be the last EPYC chips for the upcoming platform. The SP5 socket will last till 2025 which is a good timeframe to provide an update.

As for the upgrades in the architecture itself, the leaker also stated that the AMD is expected to completely redesign the L2 and L3 cache system. The Infinity Cache architecture will also see a major change. Also, HBM will become the standard across most of the lineup and the memory standard will play a huge role in next-generation EPYC CPUs. The on-board HBM hybrid design integrated within EPYC can be used to scale IPC within the same core count. One interesting and key detail is that Tom also expects Zen 5-based EPYC offerings to be amongst the first AMD EPYC server products to feature HBM designs while EPYC Venice will standardize it across multiple SKUs.

In the end, while all of this sounds great, one should remember we are talking about products that launch 3-4 years from now and a lot can change in the meantime. But it looks like EPYC Venice from AMD might indeed be a thing and we can't wait to see it in action a few years from now!

AMD EPYC CPU Families:

Family NameAMD EPYC NaplesAMD EPYC RomeAMD EPYC MilanAMD EPYC Milan-XAMD EPYC GenoaAMD EPYC BergamoAMD EPYC TurinAMD EPYC Venice
Family BrandingEPYC 7001EPYC 7002EPYC 7003EPYC 7003X?EPYC 7004?EPYC 7005?EPYC 7006?EPYC 7007?
Family Launch2017201920212022202220232024-2025?2025+
CPU ArchitectureZen 1Zen 2Zen 3Zen 3Zen 4Zen 4CZen 5Zen 6?
Process Node14nm GloFo7nm TSMC7nm TSMC7nm TSMC5nm TSMC5nm TSMC3nm TSMC?TBD
Platform NameSP3SP3SP3SP3SP5 / SP6SP5 / SP6SP5 / SP6TBD
SocketLGA 4094LGA 4094LGA 4094LGA 4094LGA 6096 (SP5)
LGA XXXX (SP6)
LGA 6096 (SP5)
LGA XXXX (SP6)
LGA 6096 (SP5)
LGA XXXX (SP6)
TBD
Max Core Count3264646496128256384?
Max Thread Count64128128128192256512768?
Max L3 Cache64 MB256 MB256 MB768 MB?384 MB?TBDTBDTBD
Chiplet Design4 CCD's (2 CCX's per CCD)8 CCD's (2 CCX's per CCD) + 1 IOD8 CCD's (1 CCX per CCD) + 1 IOD8 CCD's with 3D V-Cache (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IODTBDTBD
Memory SupportDDR4-2666DDR4-3200DDR4-3200DDR4-3200DDR5-5200DDR5-5600?DDR5-6000?TBD
Memory Channels8 Channel8 Channel8 Channel8 Channel12 Channel (SP5)
6-Channel (SP6)
12 Channel (SP5)
6-Channel (SP6)
12 Channel (SP5)
6-Channel (SP6)
TBD
PCIe Gen Support64 Gen 3128 Gen 4128 Gen 4128 Gen 4160 Gen 5 (SP5)
96 Gen 5 (SP6)
160 Gen 5 (SP5)
96 Gen 5 (SP6)
TBDTBD
TDP Range200W280W280W280W200W (cTDP 400W) SP5
70-225W SP6
320W (cTDP 400W) SP5
70-225W SP6
480W (cTDP 600W)TBD
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