AMD’s Zen 6 EPYC Venice Pictured as a 256-Core Monster, Massive Twin I/O Dies & First 2nm HPC Chip To Enter Volume Ramp

AMD has showcased its next-generation EPYC Venice CPU at the Advancing AI event, featuring a phenomenal core count of 256 based on Zen 6.

AMD Is Firing Across All Cylinders With Its Next-Gen EPYC Venice CPU Lineup: Flagship With 256 "Zen 6" Cores Pictured & It's A Monster Chip

For the next stream of data centers, CPUs are going to play a much more important role than GPUs due to the rise in Agentic AI & RL workflows. As such, all CPU vendors are releasing brand new chips that unleash the best capabilities for these workloads while leading the charts against the competition.

At Advancing AI 2026, AMD has confirmed to launch its EPYC Venice CPUs based on the Zen 6 core architecture. But while there are still a few hours left in the official presentation, the company has set banners across the Moscone Center West in San Francisco, US. One of these banners featured a very peculiar-looking chip as spotted by Computerbase, and it turns out to be none other than the flagship 256-core EPYC champion.

AMD is leveraging its brand new Zen 6 core architecture that will be used on its 6th Gen EPYC CPUs, codenamed Venice. AMD's EPYC Venice chips are the first HPC product to enter volume production on TSMC's 2nm process technology, and their readiness for Helios AI racks proves that AMD will always deliver the best of the best for its high-performance customers.

AMD Venice 256 core. pic.twitter.com/hooyKVMwBb

— Patrick Moorhead (@PatrickMoorhead) July 22, 2026

The TSMC 2nm process technology transitions from FinFET to Nanosheet transistors (GAA), and offers 10-15% higher performance at the same power, 25-30% lower power consumption at the same performance, and up to 15% higher transistor density.

AMD's 6th Gen EPYC Venice CPUs were teased earlier this year at CES, offering up to 256 cores and 512 threads with eight massive compute dies and two even larger I/O dies. You can also see that each of the eight massive CCDs features a total of 32 cores, sliced into two 16-core complexes. The IO chips in the middle look massive in size, with lots of controllers such as PCIe 6.0, UCIe, DDR5, and more.

For this chip, AMD has promised over 70% performance & efficiency improvement with its EPYC Venice CPUs, with a >30% increase in thread density.

Once again, the requirement for high-performance CPUs has risen tenfold with Agentic AI workloads. And competitors are firing across all cylinders with CPUs that are optimized around agents. Just like GPUs, NVIDIA is AMD's primary competitor in this space, which is leveraging Vera CPUs based on its custom Arm IP to power the Vera Rubin NVL72 racks. AMD's Helios AI racks powered by Zen 6 EPYC chips not only offer more cores, but faster performance and improved single-core capabilities, which is important for sustained throughput.

In early benchmarks, AMD has shown that not only do its 5th Gen Turin "Zen 5" CPUs lead against Vera, but the 6th Gen Venice "Zen 6" chips lead massively, driving more performance & offering better TCOs at a similar power scale.

AMD EPYC CPU Families:

Family Name	AMD EPYC Verano	AMD EPYC Venice	AMD EPYC Turin-X	AMD EPYC Turin-Dense	AMD EPYC Turin	AMD EPYC Siena	AMD EPYC Bergamo	AMD EPYC Genoa-X	AMD EPYC Genoa	AMD EPYC Milan-X	AMD EPYC Milan	AMD EPYC Rome	AMD EPYC Naples
Family Branding	EPYC 9007	EPYC 9006	EPYC 9005	EPYC 9005	EPYC 9005	EPYC 8004	EPYC 9004	EPYC 9004	EPYC 9004	EPYC 7004	EPYC 7003	EPYC 7002	EPYC 7001
Family Launch	2027	2026	2025	2025	2024	2023	2023	2023	2022	2022	2021	2019	2017
CPU Architecture	Zen 7	Zen 6	Zen 5	Zen 5C	Zen 5	Zen 4	Zen 4C	Zen 4 V-Cache	Zen 4	Zen 3	Zen 3	Zen 2	Zen 1
Process Node	TBD	2nm TSMC	4nm TSMC	3nm TSMC	4nm TSMC	5nm TSMC	4nm TSMC	5nm TSMC	5nm TSMC	7nm TSMC	7nm TSMC	7nm TSMC	14nm GloFo
Platform Name	SP7	SP7	SP5	SP5	SP5	SP6	SP5	SP5	SP5	SP3	SP3	SP3	SP3
Socket	TBD	TBD	LGA 6096 (SP5)	LGA 6096 (SP5)	LGA 6096	LGA 4844	LGA 6096	LGA 6096	LGA 6096	LGA 4094	LGA 4094	LGA 4094	LGA 4094
Max Core Count	TBD	96	128	192	128	64	128	96	96	64	64	64	32
Max Thread Count	TBD	192	256	384	256	128	256	192	192	128	128	128	64
Max L3 Cache	TBD	TBD	1536 MB	384 MB	384 MB	256 MB	256 MB	1152 MB	384 MB	768 MB	256 MB	256 MB	64 MB
Chiplet Design	TBD	8 CCD's (1 CCX per CCD) + 2 IOD?	16 CCD's (1CCX per CCD) + 1 IOD	12 CCD's (1CCX per CCD) + 1 IOD	16 CCD's (1CCX per CCD) + 1 IOD	8 CCD's (1CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (2 CCX's per CCD) + 1 IOD	4 CCD's (2 CCX's per CCD)
Memory Support	TBD	DDR5-12800	DDR5-6000?	DDR5-6400	DDR5-6400	DDR5-5200	DDR5-5600	DDR5-4800	DDR5-4800	DDR4-3200	DDR4-3200	DDR4-3200	DDR4-2666
Memory Channels	TBD	16-Channel (SP7)	12 Channel (SP5)	12 Channel	12 Channel	6-Channel	12 Channel	12 Channel	12 Channel	8 Channel	8 Channel	8 Channel	8 Channel
PCIe Gen Support	TBD	128-192 PCIe Gen 6	TBD	128 PCIe Gen 5	128 PCIe Gen 5	96 Gen 5	128 Gen 5	128 Gen 5	128 Gen 5	128 Gen 4	128 Gen 4	128 Gen 4	64 Gen 3
TDP (Max)	TBD	~600W	500W (cTDP 600W)	500W (cTDP 450-500W)	400W (cDP 320-400W)	70-225W	320W (cTDP 400W)	400W	400W	280W	280W	280W	200W

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