In a major development, the Biden-Harris Administration has granted the Taiwan Semiconductor Manufacturing Company (TSMC) $6.6 billion in funding under the CHIPS and Science Act to develop three chip fabrication facilities in Arizona. The award follows a preliminary grant in April, after which the Department of Commerce worked with TSMC to ensure that the firm met the requirements of the CHIPS Act. Under the funding, TSMC's three fabrication facilities at the Arizona site will manufacture semiconductors ranging from the 5-nanometer to 1.6-nanometer (A16) process family technologies.
As part of the release, President Biden asserted that the CHIPS funding shores up the American semiconductor supply chain to plug a US national security gap left open by the migration of advanced semiconductor fabrication away from the United States.
TSMC Arizona Will Manufacture 3-nanometer Chips In 2028, Outlines $6.6 Billion CHIPS Award
As part of its manufacturing plans, TSMC will start manufacturing the first chips in the Arizona site by mid-2025. The firm's subsidiary, TSMC Arizona, is responsible for production at the US facilities, and its agreement for the $6.6 billion CHIPS for America funding prohibits TSMC Arizona from buying back shares in most cases unless exempted by the agreement.
The $6.6 billion in direct funding by the Biden-Harris Administration is augmented by an additional $5 billion in loans to help TSMC Arizona meet the $65 billion capital expenditure needed to set up the three advanced manufacturing facilities in America. The capital expenditure is the"largest foreign direct investment in a greenfield project in the history of the United States," outlined President Biden.
The first of these facilities, which will start producing semiconductors in 2025, will use TSMC's 5-nanometer and 4-nanometer process technology families. These technologies are commonly used in manufacturing GPUs and other high-performance chips.
TSMC Arizona's final award follows a preliminary agreement signed between Commerce and TSMC Arizona in April. The preliminary agreement was the fifth such agreement under the CHIPS Act, and as part of the April announcement, TSMC had also outlined that it would "produce the world’s most advanced 2nm nanosheet process technology" at its second fabrication facility.
Today's announcement is the first time a release covering TSMC Arizona mentions the A16 process node. A16 is part of TSMC's future processes that cover sub-2-nanometer technologies. Like Intel, whose sub-2-nanometer technologies use similar marketing terminology, the A16 measures the marketed features of manufactured products in Angstroms instead of nanometers.
However, today's release also shifts 2-nanometer manufacturing to the third fab that is expected "to begin production by the end of the decade," according to Commerce. TSMC is currently mass-producing the 3-nanometer process technologies, and it expects to enter mass-production with the leading edge 2-nanometer process in 2025. Around the same time, Intel also plans to start its 18A production, but while Intel's 18A process will be manufactured in the US, TSMC's 2-nanometer products will be manufactured in Taiwan.
During the first stages of mass production, TSMC's leading-edge semiconductors are used in less power-intensive applications such as smartphones and notebook computers. The firm's latest 3-nanometer products are used in computers and smartphones designed by Apple, while GPUs from firms such as NVIDIA and AMD use older technologies.
NVIDIA's Hopper GPUs for artificial intelligence workloads use TSMC's N4 (or 4-nanometer), while AMD's Core Chiplet Dies (CCDs) and Accelerator Complex Dies (XCDs) in the MI300X are manufactured with the N5 (or 5-nanometer technology), according to TechInsights. Consequently, 4-nanometer and 5-nanometer production at the Arizona site in 2025 should help American companies meet their chip supplies domestically as part of attempts to shift away from the Asian ecosystem where packaging, assembly, and other operations in the supply chain also attract chip designers.
About the author: Ramish is a seasoned technology writer and editor with more than a decade of experience. He specializes in semiconductor fabrication and market analysis. With a background in finance and supply chain management - via his bachelors in Finance and a micromasters in supply chain management from MIT - Ramish combines financial rigor with deep industry insight to deliver accurate and authoritative coverage.
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