The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs

CPUs are at the heart of every computing device, from phones and laptops to servers and game consoles. Over the last 50+ years, CPU architecture has undergone dramatic transformations, driven by the relentless pursuit of performance, energy efficiency, and new computing paradigms. This article focuses on how CPUs evolved at the architectural level, from the Intel 4004 — the world's first commercial CPU — through the innovations of the late 20th century like the x86 architecture, the parallel rise of RISC designs like ARM, and finally to today’s heterogeneous multi-chiplet SoCs from the likes of Intel, AMD, and Apple.

What Is a CPU, Really?

A Central Processing Unit (CPU) (also called microprocessor, or simply just processor) is the part of a computer that executes instructions from software. At its most basic level, a CPU fetches an instruction, decodes what it’s supposed to do, executes the operation (such as an arithmetic calculation or a memory access), and then writes the result back. This is commonly known as the fetch-decode-execute cycle.

At the physical level, a CPU isn’t magic. It’s an integrated electrical circuit that's made of billions of tiny switches called transistors, typically implemented as MOSFETs (metal-oxide-semiconductor field-effect transistors) on a single piece of silicon. These transistors are created using a highly precise process centered on photolithography, where layers of a silicon wafer are coated with a light-sensitive material and exposed to ultraviolet light through patterned masks. Each exposure defines microscopic circuit patterns that are etched, doped, and layered to form the transistor structures and the intricate wiring between them. By repeating these steps dozens or even hundreds of times, manufacturers can pack enormous numbers of transistors into a chip (also called a die) no larger than a fingernail — a feat that has enabled the dramatic increases in CPU performance over the past few decades.

CPU Architecture, Detailed

Modern CPUs aren’t just a "one thing that does everything”. They’re highly organized collections of specialized components that work together to process and execute instructions as quickly as possible. At a basic level, you can think of a CPU as having a front-end, a series of storage elements, and several execution units that do the actual work.

Front-End: Fetch & Decode

Before any computation happens, the CPU must get instructions from main memory/RAM (after having been retrieved from non-volatile storage memory) and understand what they mean. The front-end is responsible for this:

• Instruction Fetcher: Retrieves the next instruction to execute from memory (often via caches).
• Instruction Decoder: Converts the raw bits of the instruction into internal signals that tell the rest of the CPU what to do next.
• Control Unit: Acts like the CPU’s conductor by orchestrating the fetch-decode-execute cycle and directing data between units based on the decoded instruction. In modern CPU designs, the control unit also guides branch prediction and speculative execution to keep pipelines busy. These steps are all part of the traditional fetch-decode-execute cycle seen in CPUs of all kinds.

Registers: The CPU’s Scratchpad

At the heart of every CPU core is a set of registers, which are super tiny, ultra-fast memory units made up of SRAM that are used to hold data and instructions the processor is currently working with. Registers are orders of magnitude faster to access than main memory or even the CPU's own caches, which is why CPUs use them so heavily during computation. Common types of registers include:

• General-purpose registers: Hold operands for arithmetic and logic operations.
• Special registers: Such as the Program Counter (PC), which tracks the next instruction to fetch, and the Instruction Register (IR), which holds the current instruction being decoded.

Arithmetic Logic Unit (ALU): Integer Math & Logic

The Arithmetic Logic Unit, or ALU, is where most of the basic computation happens:

• It handles integer arithmetic (addition, subtraction, bit shifts, etc.) and logical operations (AND/OR/XOR).
• When a program executes instructions like “add these two numbers”, the ALU is the logical circuit that performs that work.
• In superscalar and out-of-order designs, a CPU may have multiple ALUs to perform more operations in parallel per clock cycle.

Floating-Point Unit (FPU): Real-Number Math

For operations involving real numbers (decimals), CPUs use a Floating-Point Unit (FPU):

• FPUs are specialized execution units optimized for floating-point arithmetic like addition, multiplication, division, and even square roots.
• In earlier CPUs, FPUs were sometimes separate co-processors, but in nearly all modern chips, they are integrated directly into each core for performance.

Load/Store Unit (LSU): Moving Data Around

For operations involving the movement of data around the various processor blocks, a Load/Store Unit (LSU) is used:

• Executes memory access operations by loading data from memory into registers (loads) or writing register values back to memory (stores).
• Often includes load/store queues and buffering mechanisms to track memory operations and maintain correct ordering, especially in out-of-order CPUs.

Address Generation Unit (AGU): Memory Address Calculations

For operations involving memory addresses, CPUs use an Address Generation Unit (AGU):

• AGUs calculate the memory addresses used for load and store operations, determining where data should be read from or written to in memory.
• Modern CPUs often include multiple AGUs so they can compute several memory addresses simultaneously, allowing multiple memory accesses per cycle and improving overall throughput.

Vector & SIMD Units

Many contemporary CPUs also include SIMD (Single Instruction, Multiple Data) or vector units, which can perform the same operation on multiple data elements simultaneously, thus providing a huge performance boost for multimedia, encryption, and AI workloads. Examples include Intel’s SSE/AVX and ARM’s NEON extensions.

Caches & Memory Interface

While not strictly part of the core’s execution engine, cache memory is critical to performance:

• L1/L2/L3 caches sit between the CPU and main memory, holding copies of recently used data to reduce costly (mainly in terms of latency) memory accesses.
• Modern CPUs devote significant chip area to these caches because feeding data quickly to execution units is vital for high performance.

Putting It All Together

In a pipelined or superscalar CPU, all these parts must work in lockstep:

1. The front-end fetches and decodes instructions.
2. Register values are read and dispatched to the appropriate execution unit (ALU, FPU, vector unit);
3. Execution units perform the work, and results are written back into registers or main memory.
4. Caches and memory controllers reduce data access latency at every step.

Together, these components form the data path and control path that let modern CPUs chew through billions of instructions per second.

Furthermore, CPUs are also characterized by what is called an instruction set architecture (ISA), which is an abstract interface that determines the programmable interface (instructions, data types, registers, etc.) of a CPU, i.e., how software can interact with it, at the most basic level.

The Birth of x86: Intel 8086

The story of modern desktop CPUs begins in 1978, when Intel introduced the 8086 (also known as iAPX 86) microprocessor, the chip that would give rise to the still dominant x86 instruction set architecture. At the time, most consumer microprocessors were still 8-bit designs, such as Intel’s own 8080 and Zilog’s Z80. The 8086 represented a significant leap forward by introducing a 16-bit architecture, meaning its registers, arithmetic logic unit, and internal data paths were designed to operate on 16-bit words at a time.

Architecturally, the 8086 featured 16-bit internal registers and a 16-bit data bus, but it also included a 20-bit address bus, allowing the processor to access up to 1 megabyte (2^20) of memory, which was a massive amount by late 1970s standards. Because the internal registers were only 16 bits wide, Intel introduced a unique segmented memory model to generate 20-bit addresses. Memory addresses were calculated using a "segment:offset" scheme, where a 16-bit segment register was shifted left four bits and added to a 16-bit offset value to produce the final physical address. This somewhat awkward system would persist in the x86 architecture for decades.

Another notable design choice was the division of the processor into two major internal blocks: the Bus Interface Unit (BIU) and the Execution Unit (EU). The BIU handled communication with memory and I/O devices, fetching instructions, and managing address generation. Meanwhile, the EU decoded and executed instructions using the processor’s registers and ALU. To improve efficiency, the BIU included a 6-byte instruction prefetch queue, allowing the CPU to fetch upcoming instructions while the current one was being executed — an early form of instruction pipelining.

The register set itself was also carefully designed. The CPU included four general-purpose registers (AX, BX, CX, and DX), each of which could be accessed either as a full 16-bit register or split into two 8-bit halves. It also featured pointer and index registers such as SP (Stack Pointer), BP (Base Pointer), SI (Source Index), and DI(Destination Index), as well as four segment registers used for addressing memory segments.

Physically, the chip was packaged in a 40-pin dual-inline package (DIP) and contained roughly 29,000 transistors, manufactured using Intel’s HMOS (High-Performance Metal Oxide Semiconductor) process. Despite its modest transistor count by modern standards, the 8086 laid the foundation for one of the longest-lasting architectures in computing history.

Just a year later, Intel released the 8088 (AKA iAPX 88), a close variant of the 8086 that retained the same internal 16-bit architecture but used an 8-bit external data bus. This made it cheaper to integrate with existing hardware, and it was the processor ultimately chosen for the original IBM PC in 1981, cementing the x86 architecture’s place at the center of the personal computing revolution.

Early x86 Progress: 80286 to 80486

Following the successes of the 8086 and 8088, Intel continued refining the x86 architecture throughout the 1980s. Each new generation introduced important improvements that expanded memory capacity, enabled more advanced operating systems, and gradually increased performance.

Intel 80286 – Protected Mode Arrives

Released in 1982, the Intel 80286 (AKA iAPX 286) expanded the capabilities of the original x86 design while maintaining backward compatibility with 8086-compatible software. Internally, it remained a 16-bit processor, but its 24-bit address bus allowed it to access up to 16 megabytes of memory, a very significant increase over the 1 megabyte limit of earlier chips.

The most important addition was protected mode, which introduced hardware mechanisms for memory protection and multitasking. In this mode, memory segments were described through descriptor tables that allowed the processor to enforce access permissions and isolate programs from one another.

These capabilities made the 80286 a key step toward modern operating systems, though early PC software — especially MS-DOS — continued to run in the original real mode for compatibility reasons.

Intel 80386 – The 32-bit Transition

Intel’s next major leap came with the 80386 (AKA i386), which was released in 1985. This processor introduced a full 32-bit architecture, expanding registers and internal data paths while also increasing the maximum addressable memory size to 4 gigabytes.

The i386 also extended protected mode with memory paging, enabling true virtual memory systems, via specialized hardware units called the Memory Management Unit (MMU) and Translation Lookaside Buffer (TLB). Operating systems could map virtual addresses to physical memory dynamically, allowing programs to run in isolated address spaces and making advanced multitasking environments possible, not to mention massively boosting security.

These features made the 80386 the first x86 processor truly capable of supporting modern operating systems such as Windows NT and early Unix-like systems.

Intel 80486 – Integration and Pipelining

The Intel 80486 (AKA i486), introduced in 1989, retained the 32-bit architecture of the i386 but significantly improved performance through several architectural enhancements.

One major change was the integration of previously external components directly onto the CPU die. The floating-point unit (FPU), which was once a separate coprocessor, was now built into the processor itself, considerably accelerating floating-point-heavy mathematical workloads.

The i486 also introduced an 8-kilobyte on-chip level 1 (L1) cache and a pipelined execution architecture, allowing multiple instructions to overlap in execution and considerably boosting instruction throughput.

With these improvements, the i486 delivered dramatically higher performance than the i386 while maintaining full compatibility with earlier x86 software, paving the way for the next major architectural milestone: the Pentium.

The Pentium Era: Parallelism, Prediction, and Smarter Execution

By the early 1990s, CPU designers were beginning to run into the limits of simply increasing clock speeds. To continue improving performance, architects increasingly focused on extracting instruction-level parallelism (ILP), which allowed executing multiple instructions simultaneously inside the processor. Intel’s Pentium family marked a major turning point in this effort, introducing several architectural innovations that would define modern CPU design.

Pentium – Superscalar Execution and Branch Prediction

Released in 1993, the original Pentium (P5) represented a major step forward from the 80486. While earlier processors executed instructions largely one at a time, the Pentium introduced a superscalar architecture, meaning it could issue multiple instructions per clock cycle under the right conditions. The chip included two parallel integer pipelines, often referred to as the U and Y pipelines, allowing certain pairs of instructions to execute simultaneously.

Another key innovation was dynamic branch prediction, a technique designed to reduce the performance penalties associated with conditional jumps. Since modern programs contain many branches — loops, if statements, and function calls — CPUs must constantly decide which instruction to execute next. Branch prediction allows the processor to guess the likely outcome of a branch and continue fetching instructions ahead of time, keeping the pipeline full and improving overall throughput.

Together, superscalar execution and branch prediction significantly improved performance without requiring dramatic increases in clock speed.

Pentium Pro – Out-of-Order Execution and Register Renaming

The real architectural leap arrived in 1995 with the Pentium Pro, which introduced Intel’s P6 microarchitecture. While the original Pentium could execute multiple instructions in parallel, the Pentium Pro went much further by implementing out-of-order execution, allowing the processor to dynamically reorder instructions based on data availability rather than strictly following program order.

In practice, this meant the CPU could skip over instructions that were waiting for data — for example, from main memory — and execute other independent instructions first. This approach allowed the processor to keep its execution units busy and significantly improved instruction execution throughput.

To make this possible, the Pentium Pro used a technique called register renaming. The x86 architecture exposes a relatively small number of registers to software, which can create artificial dependencies when multiple instructions attempt to use the same register. Register renaming solves this by mapping these architectural registers to a larger pool of internal physical registers, eliminating false dependencies and allowing more instructions to execute in parallel.

Internally, the Pentium Pro also translated complex x86 instructions into simpler micro-operations (µops) before execution, allowing its internal execution engine to behave more like a RISC processor while still maintaining compatibility with the x86 instruction set.

Dynamic Execution and the Foundations of Modern CPUs

These innovations — superscalar pipelines, branch prediction, out-of-order execution, register renaming, and speculative execution — formed the basis of what Intel called dynamic execution. The goal was to identify independent instructions at runtime and execute them as efficiently as possible across multiple execution units.

The Pentium Pro and its successors (Pentium II and Pentium III) refined these techniques further, introducing larger caches and new SIMD instruction sets such as MMX and Streaming SIMD Extensions (SSE) to accelerate multimedia workloads. By the late 1990s, these architectural ideas had become the standard blueprint for high-performance CPUs and not just in x86 processors, but across the entire computing industry.

The GHz Race and the Pentium 4: When Clock Speed Ruled Everything

By the late 1990s and early 2000s, CPU performance marketing had converged around a single number: clock frequency. Higher megahertz (and eventually gigahertz) became the dominant metric used to compare processors, both in advertisements and in consumer perception. Intel leaned heavily into this trend with the Pentium 4, launched in 2000 and built on the new NetBurst micro-architecture.

NetBurst was designed with one primary goal: extremely high clock speeds. To achieve this, Intel dramatically lengthened the CPU’s execution pipeline to around 20 stages (and even longer in later revisions), allowing the processor to reach much higher frequencies than previous designs.

In theory, the architecture was supposed to scale toward clock speeds as high as 10 GHz.

However, this strategy came with significant trade-offs. Longer pipelines reduced the amount of work completed per clock cycle (known as instructions per cycle, or IPC) and made the processor far more sensitive to branch mispredictions, which forced the entire pipeline to flush and restart.

As a result, early Pentium 4 chips often struggled to outperform older designs in real-world workloads, and AMD’s competing Athlon processors frequently delivered better performance despite running at significantly lower clock speeds and drawing much less power.

The Pentium 4 era ultimately exposed what enthusiasts later called the “GHz myth”: clock speed alone was not a reliable indicator of CPU performance. Energy efficiency, pipeline depth, cache design, and microarchitectural improvements all played equally important roles.

NetBurst would eventually hit a wall due to power consumption and heat generation, forcing Intel to abandon the architecture in the mid-2000s and rethink its entire CPU design strategy.

The Itanium Experiment: Intel’s Attempt to Replace x86

While Intel was pushing the Pentium 4 in the desktop market, it was also pursuing a far more radical project: Itanium, a completely new 64-bit processor architecture developed with Hewlett-Packard.

Introduced in 2001, Itanium implemented a design philosophy called EPIC (Explicitly Parallel Instruction Computing). Instead of relying heavily on complex hardware to schedule instructions dynamically, EPIC expected the compiler to analyze programs and determine which instructions could run in parallel ahead of time.

In theory, this approach could enable very high instruction-level parallelism with simpler hardware. In practice, however, it placed enormous demands on compilers. Extracting large amounts of parallelism from real-world software proved extremely difficult, and many programs failed to fully utilize the processor’s execution resources.

The architecture also struggled with software compatibility. Because Itanium was not natively compatible with existing x86 applications, running legacy software often required slow emulation.

The decisive blow came in 2003, when AMD introduced x86-64 (AMD64). Instead of replacing x86 entirely, AMD extended the existing architecture to support 64-bit computing while maintaining full backward compatibility with 32-bit software. This approach allowed operating systems and applications to transition to 64-bit computing without abandoning the enormous existing x86 software ecosystem.

The industry quickly rallied around AMD’s design, and Intel eventually adopted the same approach in its own processors. While Itanium continued to exist in niche enterprise servers for years, its original goal of replacing x86 never materialized.

Multicore and Multithreading Take Hold

By the early 2000s, CPU designers were running into the power wall: increasing clock speeds further led to excessive power consumption and heat. Instead of pushing frequency higher, chipmakers began improving performance by increasing parallelism, i.e., the number of instructions that could be processed and executed per clock cycle.

The solution was the multicore processor. Instead of a single large core, CPUs began integrating multiple independent cores on the same chip, each capable of executing its own instruction stream. This allowed software to divide workloads across several cores, significantly improving performance in parallel workloads.

The Rise of Multicore CPUs

The industry shift began in the mid-2000s, with companies like AMD introducing early dual-core processors such as the Athlon 64 X2 in 2005. Multicore quickly became the new standard, with CPUs soon expanding to quad-core, eight-core, and eventually dozens of cores in modern desktop and server processors.

This approach allowed performance to scale without dramatically increasing clock speeds or power consumption.

Simultaneous Multithreading (SMT)

In addition to adding more cores, CPU designers also looked for ways to better utilize the hardware inside each core. One important technique was simultaneous multithreading (SMT), which allows a single core to execute instructions from multiple threads at the same time.

Intel introduced its implementation of SMT as Hyper-Threading in Pentium 4 processors in 2002. With Hyper-Threading, each physical core appears as two logical processors to the operating system, allowing the CPU to keep its execution units busy when one thread stalls waiting for data.

Parallelism Becomes the New Performance Frontier

Together, multicore architectures and hardware multithreading shifted CPU design toward thread-level parallelism. Instead of relying solely on faster clocks, modern processors increasingly improve performance by executing many threads simultaneously, though this only applies in workloads that actually scale to a large number of cores and threads.

This transition fundamentally reshaped both CPU design and software development, as operating systems and applications increasingly needed to be optimized for parallel workloads.

RISC vs CISC — Two Paths, One Destination

During the 1980s and 1990s, CPU designers debated two competing philosophies: CISC (Complex Instruction Set Computing) and RISC (Reduced Instruction Set Computing). CISC architectures like x86 focused on complex instructions capable of performing multiple operations in a single command, while RISC designs favored simpler instructions optimized for fast execution and efficient pipelining.

CISC Roots: x86 Architecture

The x86 architecture is classically labeled CISC (Complex Instruction Set Computer), with variable-length instructions and complex addressing modes designed to do more per instruction. While seemingly “heavy”, this complexity delivered powerful backwards compatibility, which was a crucial factor for ensuring decades of software continuity and PC industry momentum.

Despite this complexity, modern x86 CPUs internally translate instructions into simpler micro-ops that feed RISC-style execution pipelines. The result is a hybrid design that preserves compatibility while internally exploiting RISC efficiencies.

IBM POWER and the Rise of RISC

One of the most influential RISC efforts came from IBM, whose research led to the POWER microarchitecture, first introduced in 1990 for RS/6000 workstations. These processors emphasized streamlined instructions, large register files, and aggressive pipelining to achieve high performance.

POWER later evolved into PowerPC, which powered Apple Macs through the early 2000s and several major game consoles.

The Cell Processor: A Bold Experiment

An unusual descendant of IBM’s RISC lineage was the Cell Broadband Engine, which was co-developed with Sony and Toshiba. The chip combined a traditional Power core with several specialized vector processing units — called Synergistic Processing Elements (SPEs) — that were designed for highly parallel, vector/SIMD workloads.

The Cell micro-architecture delivered impressive floating-point performance and powered the PlayStation 3 and even some early petaflop supercomputers, but its complexity made it difficult for developers to fully utilize.

Convergence Over Time

Despite the intense RISC vs CISC debate, modern CPUs increasingly blur the line between the two. Today’s x86 processors often translate complex instructions into simpler internal micro-operations, meaning that internally they behave much more like RISC machines.

In practice, modern performance depends less on the instruction set itself and more on microarchitectural innovations such as powerful out-of-order engines, wide instruction decoders, accurate branch predictors, large/fast caches, and multiple execution units working on many registers and wide data paths.

Modern Advancements: Chiplets, Vector Extensions, AI, and Beyond

As traditional transistor scaling has slowed, modern CPU innovation increasingly comes from new architectural approaches and system integration, rather than simply increasing clock speeds.

Chiplets and Modular CPU Design

One major trend is the move toward chiplet-based processors. Instead of building a CPU as one large monolithic die, manufacturers assemble processors from multiple smaller dies (chiplets) that each handle specific functions such as compute cores, cache, or I/O.

This approach improves manufacturing yields, allows mixing different process nodes, and makes it easier to scale core counts. Companies like AMD popularized the strategy with its Zen-based processors, and Intel has since adopted similar modular packaging technologies.

Vector Extensions and Data Parallelism

Another key advancement is the expansion of vector and SIMD instruction sets, which allow CPUs to process many data elements with a single instruction. Extensions like SSE, AVX, AVX-512, and AMX on x86 or NEON and SVE on ARM enable large parallel operations on arrays of data, accelerating workloads such as multimedia processing, scientific simulations, and machine learning.

Beyond the Traditional CPU: The Rise of SoCs

Modern processors increasingly resemble Systems-on-a-Chip (SoCs) rather than simple CPUs. An SoC integrates many components that were once separate chips, such as GPUs, memory controllers, I/O interfaces, and specialized accelerators, all onto the same piece of silicon.

This level of integration dramatically improves power efficiency and reduces latency between components. Today’s SoCs often include AI accelerators, media engines, security processors, GPUs, and networking hardware, transforming the “CPU” from a purely general-purpose processor into a complete computing platform on a single chip.

In many ways, this shift has redefined what a processor is. Modern chips no longer consist of just CPU cores — they are heterogeneous systems designed to handle a wide variety of workloads, from graphics rendering to AI inference, all within a single integrated package.

Apple Silicon: ARM’s Big Makeover for Desktops

In 2020, Apple announced that it would transition the Mac lineup away from Intel processors to its own ARM-based Apple Silicon chips, beginning with the M1 SoC. The move started with new Macs released in late 2020 and was fully completed by 2023, marking a major architectural shift for the Mac platform.

By designing its own processors, Apple gained full control over the CPU, GPU, and system architecture, allowing it to tightly integrate hardware and software across macOS and its broader ecosystem.

One of the standout characteristics of Apple Silicon CPUs is their very high performance per clock (PPC) compared with many contemporary x86 processors. Several architectural choices contribute to this.

First, Apple’s high-performance cores use extremely wide microarchitectures. For example, the Firestorm Performance cores (P-Cores) in the M1 can decode up to eight instructions per clock cycle, significantly wider than many mainstream desktop cores, allowing them to extract large amounts of instruction-level parallelism.

Second, Apple cores include very large caches, with unusually large L1 data/instruction caches and large shared L2 caches that reduce memory latency and keep data close to the execution units.

Finally, Apple Silicon chips are designed as highly integrated systems-on-a-chip, combining CPU cores with GPUs, neural engines, and other accelerators on the same die. This tight integration reduces data movement and improves efficiency across the entire system.

Together, these design choices allow Apple Silicon processors to achieve exceptional performance-per-watt and high PPC throughput, demonstrating that ARM-based designs can compete directly with traditional desktop x86 CPUs.

Closing Thoughts

Nearly five decades after the Intel 8086, CPU architecture continues to evolve at a remarkable pace. While early progress came from higher clock speeds and smaller transistors, modern innovation increasingly comes from parallelism, specialization, and system-level design.

Several trends are likely to define the next generation of processors. Chiplet architectures and 3D stacking will continue expanding, allowing CPUs to scale to larger and more complex multi-die packages while improving manufacturing efficiency and yields. This modular approach also enables mixing different process nodes and integrating specialized accelerators more easily.

At the same time, computing is becoming increasingly heterogeneous. Modern systems combine general-purpose CPU cores with GPUs, AI engines, Digital Signal Processors (DSPs), and other specialized accelerators, each optimized for specific workloads such as graphics rendering, machine learning, or signal processing.

New instruction set ecosystems are also emerging. While x86 and ARM remain dominant in many markets, open architectures like RISC-V are gaining traction, particularly in embedded/IoT systems, AI devices, and custom silicon designs.

In many ways, the future of CPUs may look less like a single processor and more like a collection of specialized computing engines working together. Yet the core goal remains the same as it was in 1978: finding new ways to execute instructions faster, more efficiently, and at ever greater scales.

And if the history of CPU architecture has shown anything, it’s that the next breakthrough is probably already being designed in a lab somewhere.

Follow Wccftech on Google to get more of our news coverage in your feeds.