Synopsys has unveiled a massive development in the realm of mobile memory, as it announced the silicon bring-up of its LPDDR6 IP based on TSMC's N2P node.
Synopsys LPDDR6 IP Block Manages To Witness Massive Bandwidth Figures, Credited to N2P's Capabilities
For those unaware, silicon bring-up refers to the first power-on of a new chip, and in this case, particularly an IP block. This involves testing a particular product in multiple stages, such as hardware checks, power sequencing, and much more, and by the looks of it, Synopsys has managed to successfully develop a licensable building block of the LPDDR6 technology, which is claimed to feature bandwidth up to 86 GB/s, right on par with JEDEC standards, which we'll talk about ahead.
From a memory perspective, this also marks one of the first occasions for integrating TSMC's N2P process into an LPDDR6 IP block. The IP consists primarily of two main components: the controller and the PHY interface onboard. The controller focuses mainly on the JEDEC protocol engine, along with timing control and low-power states. If you are curious about how TSMC's N2P will play a role here, the node features PHY analog & I/O circuits built upon it, with N2P metal stacks and N2P I/O libraries.
More specifically, the LPDDR6 controller requires high density and speeds for tighter timing closure, and we know that the N2P is the best in this business, since the process features impressive PPA figures. This allows the memory to have a lower energy per bit, along with a smaller footprint, which ultimately enables manufacturers to leverage the technology in areas such as on-device AI and power-efficient platforms.
Talking a bit about speeds, Synopsys claims that the stack delivers 86 GB/s bandwidth, which is right around JEDEC's per-pin rate, which is also around 10.667 Gb/s. The theoretical top peak speed is set at around 14.4 GB/s per pin, which translates to a bandwidth of 115 GB/s. This means that when stacked up against LPDDR5, the LPDDR6 standard would feature massive generational upgrades, driven by the improvements brought about by TSMC's N2P technology. LPDDR6 is expected to become mainstream by next year, setting new industry standards.
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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