Next-Gen Optical Interposers To Connect Multiple Chiplets Together With Low Latency

As the chip industry navigates into the "multi-chiplet" segment, new research has presented an interesting solution for chipset-interconnect, utilizing silicon photonics such as optical interposers.

Multi-Chiplet Designs Might See Wider Adoption Through The Concept of Active Optical Interposers, Fueling Innovation In The Chip Industry

The race for chiplet designs in the CPU & GPU industry has been heating up, especially when utilizing the design technique for power-efficient solutions for the market.

For those who are unaware of what a chiplet is, it is a combination of different chips integrated into a single package, with an interconnected system that significantly contributes towards the idea of "process shrinking."

You can have multiple chiplets of the same core IP or different ones, and the designs can be mixed-matched to deliver the best suitable performance for a product segment. However, it is vital to have a suitable interconnect method, and new findings presented by CEA-Leti, a European technology research institute, show that using optical interposers, which is based on silicon photonics, might be an effective method for chiplet interconnects and will potentially significantly reduce communication delays.

Diving into details, the optical interposers are named Starac, and their utilization of silicon photonics overall conventional techniques is what makes this technology unique and capable. Starac's active optical interposers have merged electronic and photonic circuitry in one package, allowing complex data routing and processing. Apart from this, the technology contains a dedicated ONoC (Optical Network-on-Chip), which is responsible for high-speed data transmission between chiplets without requiring intermediate hops through the ring topology structure.

Starac has not yet been implemented; hence, we can't be conclusive on the performance enhancements it will bring on board, but CEA-Leti does claim that the technology will indeed reduce latency, provide higher bandwidth, and bump up the power efficiency by huge margins, eventually fueling its adoption by mainstream players. The firm is looking towards industry players to get their concept in action, but manufacturing complexities, along with high costs associated with this technique, are holding them back.

In a big compute system, there are several compute chiplets with cores and several HBMs [high-bandwidth memories],” he said. “This is true of the latest processors from Intel, AMD and Nvidia. It’s easy to go from a core to an HBM that’s close by. But if you need to go from a core to a more distant HBM, then there’s a whole sequence of operations you need to carry out to fetch the data.

With our solution, the latency would be greatly improved, because the intrinsic latency of the light being guided within our optical network-on-chip is very small compared with a trip through all the hops that would be needed in more conventional architectures.”

We hope to establish industrial partnerships within the next year or so to help us work out some of the process and packaging issues and to bring us closer to the real-word problems this technology might solve.

- Jean Charbonnier, R&D project leader at CEA-Leti

Such innovations and ideas do bring us to the point of thinking about whether Moore's Law is the only way to progress in the realm of computing or whether other possibilities exist. NVIDIA has defied Moore's Law in the past, and so have other manufacturers, by ramping up the development of other crucial factors apart from process shrinking.

News Source: EE Times

Follow Wccftech on Google to get more of our news coverage in your feeds.