Marvell has set out to utilize every bit of available memory through its Structera CXL, which compresses data to solve capacity & bandwidth challenges.
Up To 3.64x Data Compression Is Achieved With Marvell's Structera CXL Accelerators - Boosting Memory Capacity & Bandwidth
As AI workloads continue to consume massive amounts of memory, the need for high capacities and bandwidth is ever more important. But at the same time, the AI and tech segment as a whole is facing widespread memory and storage solution shortages. This has prompted tech companies to come up with innovations to mitigate the capacity/bandwidth requirements for AI.
Marvell has introduced two of its new solutions, which are part of its CXL controllers: Structera X and Structera A. These two new controllers offer compression for data that resides within the memory, and most importantly, most CXL controllers don't offer any kind of compression for the data set.
The Structera CXL controllers come embedded with a purpose-built hardware block called CDB or Compression-Decompression Block. This dedicated silicon solution operates at full bandwidth, & unlike software-based solutions, it compresses that data while it is being written to the DRAM and then decompresses when it is being read, all in real time.
This is done independent of the host CPU, which means more memory resources are available for the platform. The compression block also adheres to the specifications submitted to OCP (Open Compute Project), making it the only CXL memory controller that offers inline compression as an in-production feature.
Marvell Structera X CXL Controller
Structera X is designed as a CXL memory expansion controller with support for both DDR5 and DDR4 standards. The controller features four ARM Cortex M7 cores, the CDB block, Multi-Channel DMA, 56 MB of last-level cache, 4 DDR channels, and AES-XTS 256-bit memory (de-) encryption. The main highlights include:
- CXL 2.0 / PCIe 5.0 x16-port or 2x8-port controller
- Up to 200 GB/s memory bandwidth
- Support for up to three DIMMs per channel
- Support for >6TB of DDR5 DRAM memory capacity
- Support for >4TB of DDR4 DRAM memory capacity
- Inline LZ4 compression/decompression
- Inline XTS-AES 256-bit encryption and decryption
- Embedded hardware security module and secure boot
Marvell Structera A CXL Controller
Structera A CXL is a near-memory accelerator that optimizes memory access performance. It packs 16 Arm Neoverse V2 cores, a CDB block, four Arm Cortex M7 cores, 64 MB of last-level cache, and also offers 4 DDR channels. The main highlights include:
- CXL 2.0 / PCIe 5.0 x16-port controller
- 200 GB/s memory bandwidth
- 4 x DDR5-6400 memory channels
- Support for up to two DIMMs per channel
- 16 Arm Neoverse® V2 (Demeter) cores at 3.2 GHz
- Inline LZ4 compression/decompression
- Inline XTS-AES 256-bit encryption and decryption
- Embedded hardware security module and secure boot
Now moving to performance, the CDB is said to utilize a custom version of the LZ4 compression algorithm (a lossless algorithm), which offers a balance of high compression ratio with ultra-low latency. CDB offers one-to-many memory mapping.
Key Performance Results: Structera X 2404/2504
| Metric | Value |
| Algorithm | LZ4 |
| Page sizes supported | 4KB, 1KB |
| Max compression ratio | 64:1 (all-zero pages) |
| Compression effort levels | 0–3 (configurable) |
Compression Ratios on Structera X/A
The industry-standard mixed real-world data types achieve the following ratios on Structera hardware, which match or closely approach host LZ4 ratios:
| Data Type | Structera CDB Ratio | Host LZ4 Ratio |
| XML | 2.75X | 2.64X |
| Database (nci) | 3.64X | 3.65X |
| Source code (samba) | 2.00X | 2.07X |
| Web content (Webster) | 1.67X | 1.65X |
| Natural language (Dickens) | 1.32X | 1.32X |
| Binary/compiled (mozilla) | 1.68X | 1.73X |
The Structera CDB matches host-side LZ4 compression quality, removing the need for software-based compression and freeing up host computing resources.
As memory shortages and prices continue to intensify, solutions like Marvell's Structera CXL series will play a crucial role for the AI industry.
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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