An efficient networking chip appears to be the need of the hour as AI data centers rapidly fill up with a giga-ton of ASICs, GPUs, and orchestration-oriented CPUs. As such, it is hardly a surprise that Google now appears to have tapped Marvell to design a custom networking chip for its TPUs on one of Intel's advanced node processes.
Google is tackling the data latency conundrum head-on by tapping Marvell to design a custom networking chip for its TPUs on Intel's advanced lithography
For the benefit of those who might not be aware, a networking chip links individual ASICs to form a synchronized data-crunching behemoth. These chips primarily coordinate the flow of data between ASIC clusters, managing data congestion, operational synchronization, and data latency in real time.
Now, according to Funda AI and cited by the tipster Jukan, Google has apparently tasked Marvell with designing a custom networking chip for its TPUs. Critically, given the current bottleneck at TSMC when it comes to its advanced nodes, the proposed networking chip is likely to leverage Intel's advanced lithography process, either the 18A or the 18AP.
What's more, the networking chip is expected to enter volume production by the end of 2027, which means it will likely be paired with the upcoming Humufish TPU (TPUv8e), where Google is currently designing the ASIC's main die, with MediaTek relegated to the I/O and back-end design, and Intel handling chip fabrication and EMIB-based packaging.
Do note that Google has already deployed its TPUs across at least 11 distinct data center regions across the globe, including 2 dedicated "AI zones," which speaks volumes as to the necessity of an efficient networking chip to harmonize the operational cadence of these data centers.
Of course, this development marks another win for Marvell, which is currently riding the proverbial high horse in the wake of an emphatic endorsement from NVIDIA's CEO, who now believes it is "the next trillion-dollar company."
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