JEDEC Previews LPDDR6 Memory With SOCAMM2 Modules & 512 GB Capacities, Clearing the Path for Next-Gen AI Servers

JEDEC has previewed its LPDDR6 memory standard, powering future AI datacenters & mobile platforms with 512 GB capacities & SOCAMM2 variants.

JEDEC's LPDDR6 SOCAMM2 Modules Are Going To Be A Mouth-Watering Piece of Memory Technology For AI Datacenters

Today, JEDEC unveiled a new set of features for its upcoming LPDDR6 memory standard "JESD209-6". The new memory standard will play a vital role in powering future AI datacenters, PCs, and mobile platforms.

LPDDR6 will not just provide a more power-efficient memory solution, but it will also offer increased performance and higher capacities than existing LPDDR5 and LPDDR5X standards. Memory makers are already sampling their LPDDR6 modules to customers ahead of launch.

The main highlights of the new standard are provided below:

• Narrower per-die interface (x6) enables higher capacities: With the move to a non-binary interface width, from x16 to x24, the inclusion of x12 and an additional x6 sub-channel mode allows more dies per package and higher memory capacities per component and per channel, a critical enabler for AI-scale memory footprints.
• Flexible metadata carve‑out intended to minimize impact to peak data throughput, giving data center customers the option to balance user capacity and metadata needs according to their specific reliability requirements.
• 512 GB density on the horizon: LPDDR6 is expected to unlock densities beyond the current LPDDR5/5X maximum, a capability designed to address the ever-growing memory capacity requirements of AI training and inference workloads.
• LPDDR6 SOCAMM2 module standard in development: JEDEC is actively working on an LPDDR6-based SOCAMM2 module standard, which is being designed to carry the compact, serviceable module form factor forward and offer a clear upgrade path from today’s LPDDR5X SOCAMM2 modules.

Starting with the main features, JEDEC states that LPDDR6 will feature a vastly dense solution, with up to 512 GB capacities planned. This capacity will address the growing memory capacity requirements for AI workloads such as inferencing and training.

These higher capacities are achieved using a narrower per-die interface, increasing the bus width from x16 to x24 sub-channels. This change allows LPDDR6 to hold more memory dies per package, leading to higher capacities.

Not just that, LPDDR6 will also become a game-changer for AI datacenters, with its higher capacities, faster speeds, and more efficient designs such as SOCAMM2. The LPDDR6 SOCAMM2 modules are already in development, carrying a compact, serviceable form factor, and drop-in compatible with the existing LP5 SOCAMM2 solutions.

Press Release: LPDDR6 PIM standard in development: JEDEC is also nearing completion of a standard for LPDDR6 Processing‑in‑Memory (LPDDR6 PIM) technology, which complements the broader LPDDR6 roadmap, a next‑generation memory solution intended to address the rapidly increasing performance and energy‑efficiency requirements of edge and data‑center inference workloads. By integrating processing capability directly within LPDDR6 memory, LPDDR6 PIM reduces data movement between memory and compute, enabling higher inference performance and lower power consumption while maintaining the efficiency advantages of LPDDR‑based designs.

“Stay tuned for more details on the next version of LPDDR6 as well as LPDDR6 PIM and LPDDR6 SOCAMM2,” said Mian Quddus, JEDEC Board of Directors Chairman.  “The subcommittee continues to evaluate features for inclusion in these standards when they are published.”

JEDEC encourages companies to join and help shape the future of JEDEC standards.  JEDEC membership provides access to pre-publication proposals and early insights into active projects such as LPDDR6, LPDDR6 PIM, LPDDR6 SOCAMM2, and more. 

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