Inference is the next area of focus for compute providers, and after the NVIDIA-Groq partnership, the AI industry has realized it needs far more than just GPUs. This has led to a new pair emerging: Intel and SambaNova.
Intel's Xeon 6 CPUs Will Act as the Host For Agentic Systems, Backed By SambaNova's SN50 Chip For Decode
At this year's GTC, we saw NVIDIA talking about disaggregated inference, and how it has become important for them as a manufacturer to shift from their 'GPU-only' mentality, and instead bring in a relatively newer form of compute units into the infrastructure race. With the Groq licensing agreement, we saw the SRAM-based LPUs debut in Rubin's LPX racks, and now Intel and SambaNova have decided to experiment with something similar, unveiling a new "inference architecture" featuring SambaNova's RDUs with Intel's Xeon 6 CPUs.
SambaNova today announced the next phase of its collaboration with Intel: a heterogeneous hardware solution that combines GPUs for prefill, Intel® Xeon® 6 processors as both host and “action” CPUs, and SambaNova RDUs for decode to deliver premium inference for the most demanding Agentic AI applications.
- SambaNova
This arrangement aims to target RDUs for decode workloads, with GPUs handling prefill work and Xeon 6 CPUs handling tasks such as orchestration and general-purpose work. The Intel-SambaNova partnership doesn't lock in a specific hyperscaler for the GPU option, meaning you could integrate ASICs in this configuration as well, though SambaNova didn't go into much detail about GPU-specific performance. SambaNova will integrate their SN50 units, which we'll discuss in a bit, and, along with this, the firm says they found Xeon 6 CPUs as the ideal for "end‑to‑end coding agent workflows" compared to ARM options.
Let's talk about the SN50 chip. The solution, revealed in early 2026, features the company's fifth-gen RDU units, with a combination of DRAM, SRAM, and HBM onboard. The SN50 features 2TB of DDR5 memory, along with 64 GB HBM3 and 520 MB SRAM, and, if you have guessed it by now, the idea of having such a memory architecture onboard is to provide minimal latency, high throughput, and sheer capacity. The SN50 is probably the only accelerator to feature such a memory layout, and according to the manufacturer, the DRAM + SRAM + HBM combo creates 'agentic caching'.
On a more general level, the primary difference between Intel's approach with SambaNova and NVIDIA's is that the former focuses more on a 'safer' bet, given that it doesn't need to provide a hefty underlying infrastructure for disaggregated inference. For hyperscalers looking for a more modular rack-scale offering that targets the "prefill + decode" breakdown, the Intel-SambaNova option is a decent bet. We were expecting Intel to go much deeper with RDU integration, but it seems, for now, it might be limited to just the Xeon CPU as the host option.
Intel's CEO has participated in SambaNova's latest funding round, and Lip-Bu is also an early investor in the company. There were plans to acquire them as well, but they were reportedly halted after a board disagreement, which is why Intel has settled on being a funding participant.
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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