The die sizes of Intel's Nova Lake compute tiles have been revealed, with the base die measuring slightly smaller than Arrow Lake's compute tile.
Intel's Nova Lake bLLC Compute Tile Measures Slightly Bigger Than Standard Variant, Dual Compute Tile Variants To Take 300mm² of Space on Package
Details regarding Intel's Nova Lake CPUs continue to be shared online. The latest information comes from HXL regarding the die sizes of two compute tiles based on the 8+16 configuration.
As we know from earlier reports, Intel's Nova Lake CPUs, both desktops and laptops, will make use of an 8+16 configuration, which will then be cut down to form various SKUs. There's also going to be a 4+8 SKU for entry-level and mainstream models. All compute tiles are being fabricated on TSMC's N2 process technology, so the compute tile on Nova Lake isn't getting 18A treatment like Panther Lake chips. There is still a slight possibility that we will see an 18A compute tile as the rumored roadmap reveals, but for now, we have two N2 dies.
Starting with the details, the Intel Nova Lake CPUs will feature 8 P-Cores based on the Coyote Cove and 16 E-Cores based on the Arctic Wolf E-Core architecture. The chips will also house 4 LPE cores on a low-power island, which cannot be overclocked but can be used primarily (both P/E cores disabled) or alongside the E-Core clusters. The P-Cores are also being arranged in 2 per cluster with 4 MB of L2 cache per cluster.
A single standard Nova Lake die with 8 P-Cores, 16 E-Cores, and 4 LPE cores will measure around 110mm², which is slightly smaller than the 117.2mm² die size of Arrow Lake's compute tile. But there's also the big cache or bLLC variants, which add 144 MB of cache per compute tile. The bLLC 8+16 die is going to be around 36.6% bigger, measuring around 150mm² and 28% larger than Arrow Lake's compute tile.
This also gives us early info on the dual compute tile variants. The standard "Non-bLLC" variants with two of the compute tiles will measure around 220mm², and the bLLC variants with up to 52 cores and 288 MB of L3 cache (320 MB L2 + L3) will measure close to 300mm².
That's quite a big chunk of die space for the compute tile alone, but the good thing is that all of this will be allocated within the same package area and will be featured on the same socket. So it's not like the bLLC or dual compute tile variants will require a different platform or bigger socket to run on.
We can also compare the compute tile dies to AMD's upcoming Zen 6 and existing Zen 5 dies. Currently, AMD offers 8 cores per CCD with the Zen 5 architecture. These dies measure 71mm². For Zen 6, AMD is expected to offer up to 12 cores per CCD in an estimated die size of 76mm².
So if we compare the dies, the standard 8+16 or 24 core Intel Nova Lake tile is going to measure 55% bigger than Zen 5 CCDs while offering 3 times the core count. Compared to Zen 6, Intel's Nova Lake-S compute tile will measure 44% bigger while offering twice the core count. Just like that, the bLLC die is going to be bigger while offering more cores, but the difference is that AMD doesn't need to expand the die area to feature extra cache. They have X3D stacking technologies, which means that the extra cache sits on or below the CCD. Intel does have the tech to embed extra cache within the base tile, but that is not being implemented in Nova Lake.
So the comparisons are as follows:
- Intel Nova Lake 8+16 (Standard Compute Tile) = ~110mm²
- Intel Nova Lake 8+16+144 MB (bLLC Compute Tile) = ~150mm²
- Intel Nova Lake 16+32 (Dual Compute Tile) = ~220mm²
- Intel Nova Lake 16+32+288 MB (bLLC Dual Compute Tile) = ~300mm²
- AMD Zen 5 8 Core CCD + 32 MB/64 MB X3D = ~71mm²
- AMD Zen 6 12 Core CCD + 48 MB/TBD MB X3DL3 = ~76mm²
That's all the information we have on Intel Nova Lake-S Desktop CPUs for today, but it looks like things are clearing up, and we are getting a more detailed picture of what the new platform and processors are going to look like. Once again, Intel's Nova Lake-S CPUs, along with the 900-series motherboards, are scheduled to launch later this year and will be competing against AMD's Zen 6-based Ryzen offerings, which also offer new architectural and platform innovations, so quite an interesting battle is being brewed up for 2H 2026.
Nova Lake-S vs Arrow Lake-S
| Family | Nova Lake-S | Arrow Lake-S |
|---|---|---|
| Core Count (Max) | 52 | 24 |
| Thread Count (Max) | 52 | 24 |
| Max P-Cores | 16 | 8 |
| Max E-Cores | 32 | 16 |
| Max LP-E Cores | 4 | 0 |
| Max Cache (L2+L3) | 160-320 MB | 76 MB |
| Max bLLC Cache | 144-288 MB | N/A |
| DDR5 (1DPC 1R) | 8000 MT/s | 7200-6400 MT/s |
| PCIe 5.0 Lanes (Max) | 36 | 24 |
| PCIe 4.0 Lanes (Max) | 16 | 4 |
| Socket Support | LGA 1954 | LGA 1851 |
| Max TDP (PL1) | 125-175W | 125W |
| Max Power | ~700W (Dual) ~350W (Single) | ~400W |
| Launch | 2H 2026 | 1H 2026 |
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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