Intel's advancements with its AVX (Advanced Vector Extensions) instruction sets are definitely the way to go in the future, & now the next-gen AVX10 has started to gain support at GNU Assembler.
Intel's AVX10 Instruction Set Will Bring Bumped up Computational Performance, Credits to Use of Both P/E Cores
Before going into the crux, knowing about AVX instructions becomes necessary. For an ordinary user, they won't sound very interesting however, the instructions are vital for professionals, especially in the HPC industry. They enable highly parallel floating-point and vectorized operations, leading to significant performance improvements in various computational workloads. While the previous AVX-512 instructions brought in decent performance, the AVX-10 is all set to take future CPUs to a whole new level when it comes to relevant workloads.
Another important aspect that makes the release of AVX10 crucial for Intel CPUs is the instruction's adoption to work with both P/E cores, which feature in Intel's hybrid architecture. The utilization of both types of cores will result in a large bump in performance as well, especially in vectorizable applications.
Phoronix reports that after the initial announcement, AVX-10 development was initiated in the GCC compiler and now we have finally seen "bits" specific to the new instruction set (AVX 10.1) being uploaded on GNU Assembler by the German-based open-source company SUSE. Here is what their developer has to say:
Since this is merely a re-branding of certain AVX512* features, there's little code to be added.
The main aspect here are new testcases. In order to be able to re-use some of the existing testcases, several of them need their start symbols adjusted. Note that 256- and 128-bit tests want adding here, as these need to work right away. Subsequently they'll gain vector length constraints.
-SUSE's Jan Beulich
While I realize that this news isn't a significant development, tiny steps like these contribute to something great. The new AVX-10 instruction set could bring a decent performance uplift in computational applications for next-gen CPUs, and they could feature with Intel's upcoming Meteor Lake as well, which would expand the possibilities of the lineup being adopted by the industry. We have yet to see how the AVX-10 instruction is an upgrade from the previous generations, but on paper, the gap seems wide enough.
News Source: Phoronix
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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