Intel Foundry has showcased "breakthrough" developments in the realm of transistor and packaging technologies, revealing material and silicon innovation.
Intel Foundry Showcases "Subtractive Ruthenium" & New Transistor Technologies To Ensure Node Scalability
[Press Release]: Today at the IEEE International Electron Devices Meeting (IEDM) 2024, Intel Foundry unveiled breakthroughs to help drive the semiconductor industry forward into the next decade and beyond. Intel Foundry showcased new material advancements that help improve interconnections within a chip, resulting in up to 25% capacitance by using subtractive ruthenium.
Intel Foundry also was the first to report a 100x throughput improvement using a heterogeneous integration solution for advanced packaging to enable ultra-fast chip-to-chip assembly. To further drive gate-all-around (GAA) scaling, Intel Foundry demonstrated work with silicon RibbonFET CMOS and with gate oxide module for scaled 2D FETs for improved device performance.
Why It Matters: As the industry heads toward putting 1 trillion transistors on a chip by 2030, breakthroughs in transistor and interconnect scaling – multiplied by future advanced packaging capabilities – are critical for delivering on the endless appetite for more energy-efficient, high-performin,g and cost-effective computing applications such as AI.
The industry will also require additional support in the form of new materials to augment Intel Foundry’s PowerVia backside power delivery in relieving interconnect crowding and for continued scaling, which is vital to the continuation of Moore’s Law and driving the semiconductor forward into new eras for AI.
How We are Doing It: Intel Foundry has identified several paths that solve anticipated limitations of copper transistors in interconnect scaling for future nodes, improve upon existing assembly techniques, and continue to define and shape the transistor roadmap for gate-all-around scaling and beyond:
- Subtractive Ruthenium (Ru): To help improve the performance and interconnections within chips, Intel Foundry showcased subtractive ruthenium, a new key alternative metallization material that uses thin film resistivity along with airgaps to deliver a significant advancement in interconnect scaling. The team was first to demonstrate, in R&D test vehicles, a practical, cost-efficient and high-volume manufacturing compatible subtractive Ru integrated process with airgaps that does not require expensive lithographic airgap exclusion zones around vias, or self-aligned via flows that require selective etches. The implementation of airgaps with subtractive Ru provided up to 25% of line-to-line capacitance reduction at pitches less than or equal to 25 nanometers (nm), illustrating the benefits of subtractive Ru as a metallization scheme to replace copper damascene in tight pitch layers. This solution could be seen on Intel Foundry’s future nodes.
- Selective Layer Transfer (SLT): To enable up to 100x higher throughput for ultra-fast chip-to-chip assembly in advanced packaging, Intel Foundry is the first to demonstrate Selective Layer Transfer (SLT), a heterogeneous integration solution that enables ultra-thin chiplets with much better flexibility to enable smaller die sizes and higher aspect ratios versus traditional chip-to-wafer bonding. This allows higher functional density and leads to a more flexible and cost-efficient solution for hybrid or fusion bonding of specific chiplets from one wafer to another. This solution offers a more efficient and flexible architecture for AI applications.
- Silicon RibbonFET CMOS: To push gate-all-around RibbonFET silicon scaling to its limits, Intel Foundry showcased silicon RibbonFET CMOS (complementary metal oxide semiconductor) transistors at a gate length of 6 nm with industry-leading short channel effects and performance at aggressively scaled gate length and channel thickness. This advancement paves the way for continued gate length scaling, one of the key foundational cornerstones of Moore’s Law.
- Gate Oxide for Scaled GAA 2D FETs: To further accelerate gate-all-around innovation beyond CFET, Intel Foundry showcased its work on the fabrication of GAA 2D NMOS and PMOS transistors with scaled gate length down to 30 nm with a specific focus on gate oxide (GOx) module development. The research reports on the industry’s investigation of two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors, which may be a future replacement for silicon in advanced transistor processes.
Additionally, Intel Foundry continued to advance research with the industry’s first 300 millimeters (mm) gallium nitride (GaN) technology, an emerging technology for power and radio frequency (RF) electronics that can deliver higher performance and sustain higher voltages and temperatures than silicon.
This is the industry’s first high-performance scaled enhancement-mode GaN MOSHEMTs (metal-oxide-semiconductor high electron mobility transistors), fabricated on a 300 mm GaN-on-TRSOI (“trap-rich” silicon-on-insulator) substrate. Advanced-engineered substrates like GaN-on-TRSOI can achieve better performance in applications such as RF and power electronics by reducing signal loss and achieving better signal linearity, enabling advanced integration schemes that may be realized through backside substrate processing.
More from IEDM 2024: At the conference, Intel Foundry also laid out its vision for the future of advanced packaging and transistor scaling to meet demands across applications including AI. Three key thrusts for innovation were identified to help drive the next decade toward more power-efficient AI.
- Advanced memory integration to eliminate capacity, bandwidth, and latency bottlenecks.
- Hybrid bonding for interconnect bandwidth optimization.
- Modular system expansion with corresponding connectivity solutions.
Intel Foundry also shared a call to action to develop critical and revolutionary innovations for continued transistor scaling for the trillion-transistor era. Intel Foundry outlined how developing a transistor capable of ultra-low voltage operation (less than 300 millivolts) will help address increasing thermal bottlenecks and result in dramatic improvements in energy consumption and thermal dissipation.
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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